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1; RUN: llc -O2 -mtriple=hexagon < %s2; REQUIRES: asserts3 4; Test that the final instruction ordering code does not result in infinite5; recursion (a segmentation fault). The problem is that the order heuristics6; did not properly take into account the stage in which an instruction is7; scheduled.8 9%0 = type { %1, %4, %9, %28 }10%1 = type { i8, [32 x %2] }11%2 = type { i8, %3, i8, i8, i16, i8, [20 x i16], [20 x i16] }12%3 = type { i16, i8 }13%4 = type { i8, [64 x %5], [64 x ptr] }14%5 = type { i8, i8, ptr, %6 }15%6 = type { %7 }16%7 = type { ptr, %3, i8, i8, i8, i8, i16, i8, i8, i8, i16, i32, i8, [3 x i8], [3 x i16], i16, i8, i16, i8, %8, i16, i8, i16 }17%8 = type { i8, i8 }18%9 = type { i8, i8, ptr, i8, [8 x ptr], i8, i8, i8, i8, i8, ptr, i8, ptr, i8, i8, i8, i8, i8, i8, i8, i8, i32, i8, i32, i32, i32, i32, i32, i32, i32, i8, i8, i16, i8, ptr, i8, i8, i8, i8, i8, i8 }19%10 = type { i8, i8, i8, i8, i8, %11, %12, %13, %14 }20%11 = type { i8, i16, i16 }21%12 = type { i8, i16, ptr }22%13 = type { i8, i16 }23%14 = type { %15, %20, %25 }24%15 = type { i8, i8, %16, i8, [18 x %17] }25%16 = type { i8, i16, i16 }26%17 = type { i8, i8, [10 x %3], [10 x i16], [10 x i16], [10 x i8], ptr }27%18 = type { %19, i16, i16, %19, i16 }28%19 = type { i16, i16, i16, i8 }29%20 = type { i8, i8, %21 }30%21 = type { ptr, %22, %23 }31%22 = type { %3, i8, i8, i16, i16, i16, i8, i16 }32%23 = type { [2 x %24], [4 x i8] }33%24 = type { i8, %3, i16, i16, i16, i16, ptr }34%25 = type { i8, i8, [8 x %26] }35%26 = type { ptr, %27, %24 }36%27 = type { %3, i8, i16, i16, i16 }37%28 = type { [2 x %29], [2 x i16], i8, ptr, i16, i8, i8, ptr, ptr, ptr, ptr, [3 x ptr], i8, [2 x i8], i8, i8, [2 x i8], [2 x i8], [3 x i8] }38%29 = type <{ %30, i8, [1000 x i8] }>39%30 = type { i16, i16, [2 x i32] }40%31 = type <{ i8, i8, i16, i8 }>41%32 = type <{ i16, i16, i8, i16 }>42%33 = type <{ i8, i8, i16, i16, i16, i8, i16, i16 }>43%34 = type <{ i8, i8, i16, i16, i8, i16, i8, i8, i32, i16, i16, i16 }>44 45@g0 = external global [2 x %0], align 846 47; Function Attrs: nounwind ssp48define void @f0() #0 {49b0:50 br label %b151 52b1: ; preds = %b1, %b053 %v0 = phi i32 [ 0, %b0 ], [ %v5, %b1 ]54 %v1 = getelementptr inbounds [2 x %0], ptr @g0, i32 0, i32 undef, i32 1, i32 1, i32 %v055 %v2 = getelementptr inbounds [2 x %0], ptr @g0, i32 0, i32 undef, i32 1, i32 2, i32 %v056 store ptr %v1, ptr %v2, align 457 %v3 = getelementptr inbounds [2 x %0], ptr @g0, i32 0, i32 undef, i32 1, i32 1, i32 %v0, i32 358 store ptr %v1, ptr %v3, align 459 %v5 = add nuw nsw i32 %v0, 160 %v6 = icmp eq i32 %v5, 6461 br i1 %v6, label %b2, label %b162 63b2: ; preds = %b164 ret void65}66 67attributes #0 = { nounwind ssp "target-cpu"="hexagonv55" }68