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1; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true -terminal-rule=0 | FileCheck %s2 3; Test that the pipeliner cause an assert and correctly pipelines the4; loop.5 6; CHECK: loop0(.LBB0_[[LOOP:.]],7; CHECK: .LBB0_[[LOOP]]:8; CHECK: [[REG0:r([0-9]+)]] = sath([[REG1:r([0-9]+)]])9; CHECK: memh(r{{[0-9]+}}++#2) = [[REG0]].new10; CHECK: [[REG1]] =11; CHECK: endloop012 13define void @f0(ptr nocapture %a0, ptr nocapture readonly %a1, float %a2, i32 %a3) {14b0:15 %v0 = icmp sgt i32 %a3, 016 br i1 %v0, label %b1, label %b217 18b1: ; preds = %b1, %b019 %v1 = phi i32 [ %v11, %b1 ], [ 0, %b0 ]20 %v2 = phi ptr [ %v10, %b1 ], [ %a0, %b0 ]21 %v3 = phi ptr [ %v4, %b1 ], [ %a1, %b0 ]22 %v4 = getelementptr inbounds float, ptr %v3, i32 123 %v5 = load float, ptr %v3, align 4, !tbaa !024 %v6 = fmul float %v5, %a225 %v7 = tail call i32 @llvm.hexagon.F2.conv.sf2w(float %v6)26 %v8 = tail call i32 @llvm.hexagon.A2.sath(i32 %v7)27 %v9 = trunc i32 %v8 to i1628 %v10 = getelementptr inbounds i16, ptr %v2, i32 129 store i16 %v9, ptr %v2, align 2, !tbaa !430 %v11 = add nuw nsw i32 %v1, 131 %v12 = icmp eq i32 %v11, %a332 br i1 %v12, label %b2, label %b133 34b2: ; preds = %b1, %b035 ret void36}37 38; Function Attrs: nounwind readnone39declare i32 @llvm.hexagon.A2.sath(i32) #040 41; Function Attrs: nounwind readnone42declare i32 @llvm.hexagon.F2.conv.sf2w(float) #043 44attributes #0 = { nounwind readnone }45 46!0 = !{!1, !1, i64 0}47!1 = !{!"float", !2, i64 0}48!2 = !{!"omnipotent char", !3, i64 0}49!3 = !{!"Simple C/C++ TBAA"}50!4 = !{!5, !5, i64 0}51!5 = !{!"short", !2, i64 0}52