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1; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s2 3; Test that when we order instructions in a packet we check for4; order dependences so that the source of an order dependence5; appears before the destination.6 7; CHECK: loop0(.LBB0_[[LOOP:.]],8; CHECK: .LBB0_[[LOOP]]:9; CHECK: = memw10; CHECK: = memw11; CHECK: memw({{.*}}) =12; CHECK: = memw13; CHECK: = memw14; CHECK: endloop015 16@g0 = external hidden unnamed_addr constant [19 x i8], align 117 18; Function Attrs: nounwind optsize19declare i32 @f0(ptr nocapture readonly, ...) #020 21; Function Attrs: nounwind optsize22declare void @f1(ptr, ptr, ptr nocapture readnone) #023 24; Function Attrs: argmemonly nounwind25declare ptr @llvm.hexagon.circ.stw(ptr, i32, i32, i32) #126 27; Function Attrs: nounwind optsize28define void @f2(ptr %a0, ptr %a1, ptr %a2) #0 {29b0:30 %v0 = alloca i32, align 431 call void @f1(ptr %a2, ptr %a0, ptr %v0) #232 br label %b133 34b1: ; preds = %b1, %b035 %v2 = phi i32 [ 0, %b0 ], [ %v13, %b1 ]36 %v3 = phi ptr [ %a2, %b0 ], [ %v16, %b1 ]37 %v4 = phi i32 [ 0, %b0 ], [ %v14, %b1 ]38 %v5 = load i32, ptr %a1, align 4, !tbaa !039 %v6 = add nsw i32 %v2, %v540 %v7 = load i32, ptr %v3, align 4, !tbaa !041 %v8 = tail call ptr @llvm.hexagon.circ.stw(ptr %a1, i32 %v7, i32 150995968, i32 4) #342 %v10 = load i32, ptr %v3, align 4, !tbaa !043 %v11 = add nsw i32 %v6, %v1044 %v12 = load i32, ptr %v8, align 4, !tbaa !045 %v13 = add nsw i32 %v11, %v1246 %v14 = add nsw i32 %v4, 147 %v15 = icmp eq i32 %v14, 248 %v16 = getelementptr i32, ptr %v3, i32 149 br i1 %v15, label %b2, label %b150 51b2: ; preds = %b152 %v17 = tail call i32 (ptr, ...) @f0(ptr @g0, i32 %v13) #453 ret void54}55 56attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" }57attributes #1 = { argmemonly nounwind }58attributes #2 = { optsize }59attributes #3 = { nounwind }60attributes #4 = { nounwind optsize }61 62!0 = !{!1, !1, i64 0}63!1 = !{!"int", !2, i64 0}64!2 = !{!"omnipotent char", !3, i64 0}65!3 = !{!"Simple C/C++ TBAA"}66