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1; RUN: llc -O2 -mtriple=hexagon < %s2; REQUIRES: asserts3 4%0 = type { [2 x [8 x [16 x i8]]], [4 x [16 x ptr]] }5%1 = type { i32, i32, i8, i8, %2, ptr }6%2 = type { i32, i32, ptr, i8, i16, i16, i8 }7%3 = type { i16, i16, %4, i16, i8, i16, %5, i32 }8%4 = type { i32 }9%5 = type { i16, i16 }10%6 = type { ptr }11%7 = type { [16 x i16], [16 x i16] }12 13; Function Attrs: norecurse nounwind14define void @f0(ptr nocapture %a0) #0 {15b0:16 br label %b117 18b1: ; preds = %b1, %b019 %v0 = phi i32 [ 0, %b0 ], [ %v6, %b1 ]20 %v1 = getelementptr inbounds %0, ptr %a0, i32 0, i32 1, i32 3, i32 %v021 %v3 = load i32, ptr %v1, align 422 store i32 %v3, ptr undef, align 423 %v4 = getelementptr inbounds %0, ptr %a0, i32 0, i32 1, i32 0, i32 %v024 store i32 %v3, ptr %v4, align 425 %v6 = add nuw nsw i32 %v0, 126 %v7 = icmp eq i32 %v6, 1627 br i1 %v7, label %b2, label %b128 29b2: ; preds = %b130 ret void31}32 33attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }34