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1; RUN: llc -mtriple=hexagon -debug-only=pipeliner < %s -o - 2>&1 -pipeliner-experimental-cg=true | FileCheck %s2; REQUIRES: asserts3 4; Test that there is a chain edge between two dependent Phis.5; The pipeliner tries to remove chains between unrelated Phis, but6; was too aggressive in some cases. When this happens the two Phis may get7; scheduled too far apart. In this case, the second Phi was scheduled in8; the next stage.9 10; CHECK: SU([[SU1:[0-9]+]]): %14:intregs = PHI %{{[0-9]+}}:intregs, %bb.0, %{{[0-9]+}}:intregs, %bb.111; CHECK: Successors:12; CHECK: SU({{.*}}): Data Latency=013; CHECK: SU([[SU2:[0-9]+]]): Data Latency=014; CHECK: SU([[SU2]]): %{{[0-9]+}}:intregs = PHI %{{[0-9]+}}:intregs, %bb.0, %14:intregs, %bb.115; CHECK: Predecessors:16; CHECK: SU([[SU1]]): Data Latency=017 18%s.0 = type { i16, i8, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr, [2 x i32], ptr, ptr, ptr, %s.1, ptr, [8 x i8], i8 }19%s.1 = type { i32, i16, i16 }20%s.2 = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 }21 22@g0 = global i32 0, align 423@g1 = global i32 0, align 424@g2 = global i32 0, align 425@g3 = global i32 0, align 426@g4 = global i32 0, align 427@g5 = common global i32 0, align 428@g6 = external global %s.029@g7 = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 130 31; Function Attrs: nounwind32declare i32 @f0(ptr nocapture, ptr nocapture readonly, ...) #033 34; Function Attrs: nounwind35define void @f1(ptr nocapture %a0, ptr nocapture readonly %a1, ptr nocapture readonly %a2, i16 signext %a3) #0 {36b0:37 %v0 = load i32, ptr %a2, align 438 %v1 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v0, i32 2)39 %v2 = tail call i32 @llvm.hexagon.A2.sath(i32 %v1)40 store i32 0, ptr @g5, align 441 %v3 = load i32, ptr @g0, align 442 %v4 = load i32, ptr @g1, align 443 %v5 = load i32, ptr @g2, align 444 %v6 = load i32, ptr @g3, align 445 %v7 = load i32, ptr @g4, align 446 br label %b147 48b1: ; preds = %b1, %b049 %v8 = phi i32 [ %v7, %b0 ], [ %v52, %b1 ]50 %v9 = phi i32 [ %v6, %b0 ], [ %v50, %b1 ]51 %v10 = phi i32 [ %v5, %b0 ], [ %v46, %b1 ]52 %v11 = phi i32 [ %v4, %b0 ], [ %v44, %b1 ]53 %v12 = phi i32 [ %v3, %b0 ], [ %v38, %b1 ]54 %v13 = phi i32 [ 0, %b0 ], [ %v53, %b1 ]55 %v14 = phi ptr [ %a2, %b0 ], [ %v26, %b1 ]56 %v15 = phi ptr [ %a1, %b0 ], [ %v19, %b1 ]57 %v16 = phi i32 [ %v2, %b0 ], [ %v32, %b1 ]58 %v17 = phi i32 [ 0, %b0 ], [ %v25, %b1 ]59 %v18 = phi i32 [ 0, %b0 ], [ %v16, %b1 ]60 %v19 = getelementptr inbounds i32, ptr %v15, i32 161 %v20 = load i32, ptr %v15, align 462 %v21 = tail call i32 @llvm.hexagon.A2.asrh(i32 %v20)63 %v22 = shl i32 %v21, 1664 %v23 = ashr exact i32 %v22, 1665 %v24 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v23, i32 2)66 %v25 = tail call i32 @llvm.hexagon.A2.sath(i32 %v24)67 %v26 = getelementptr inbounds i32, ptr %v14, i32 168 %v27 = load i32, ptr %v14, align 469 %v28 = tail call i32 @llvm.hexagon.A2.asrh(i32 %v27)70 %v29 = shl i32 %v28, 1671 %v30 = ashr exact i32 %v29, 1672 %v31 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v30, i32 2)73 %v32 = tail call i32 @llvm.hexagon.A2.sath(i32 %v31)74 %v33 = shl i32 %v17, 1675 %v34 = ashr exact i32 %v33, 1676 %v35 = tail call i32 @llvm.hexagon.M2.mpy.nac.sat.ll.s1(i32 %v12, i32 %v34, i32 %v34)77 %v36 = shl i32 %v16, 1678 %v37 = ashr exact i32 %v36, 1679 %v38 = tail call i32 @llvm.hexagon.M2.mpy.nac.sat.ll.s1(i32 %v35, i32 %v37, i32 %v37)80 store i32 %v38, ptr @g0, align 481 %v39 = shl i32 %v25, 1682 %v40 = ashr exact i32 %v39, 1683 %v41 = tail call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v11, i32 %v40, i32 %v34)84 %v42 = shl i32 %v32, 1685 %v43 = ashr exact i32 %v42, 1686 %v44 = tail call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v41, i32 %v43, i32 %v37)87 store i32 %v44, ptr @g1, align 488 %v45 = tail call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v10, i32 %v43, i32 %v34)89 %v46 = tail call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v45, i32 %v40, i32 %v37)90 store i32 %v46, ptr @g2, align 491 %v47 = tail call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v9, i32 %v40, i32 0)92 %v48 = shl i32 %v18, 1693 %v49 = ashr exact i32 %v48, 1694 %v50 = tail call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v47, i32 %v43, i32 %v49)95 store i32 %v50, ptr @g3, align 496 %v51 = tail call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v8, i32 %v43, i32 0)97 %v52 = tail call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v51, i32 %v40, i32 %v49)98 store i32 %v52, ptr @g4, align 499 %v53 = add nsw i32 %v13, 1100 %v54 = icmp slt i32 %v53, 4101 store i32 %v53, ptr @g5, align 4102 br i1 %v54, label %b1, label %b2103 104b2: ; preds = %b1105 %v55 = tail call i32 (ptr, ptr, ...) @f0(ptr @g6, ptr @g7, i32 %v46) #2106 %v56 = load i32, ptr @g2, align 4107 %v57 = getelementptr inbounds %s.2, ptr %a0, i32 0, i32 5108 store i32 %v56, ptr %v57, align 4, !tbaa !0109 ret void110}111 112; Function Attrs: nounwind readnone113declare i32 @llvm.hexagon.A2.sath(i32) #1114 115; Function Attrs: nounwind readnone116declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #1117 118; Function Attrs: nounwind readnone119declare i32 @llvm.hexagon.A2.asrh(i32) #1120 121; Function Attrs: nounwind readnone122declare i32 @llvm.hexagon.M2.mpy.nac.sat.ll.s1(i32, i32, i32) #1123 124; Function Attrs: nounwind readnone125declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32, i32, i32) #1126 127attributes #0 = { nounwind "target-cpu"="hexagonv55" }128attributes #1 = { nounwind readnone }129attributes #2 = { nounwind }130 131!0 = !{!1, !2, i64 20}132!1 = !{!"", !2, i64 0, !2, i64 4, !2, i64 8, !2, i64 12, !2, i64 16, !2, i64 20, !2, i64 24, !2, i64 28, !2, i64 32}133!2 = !{!"int", !3, i64 0}134!3 = !{!"omnipotent char", !4, i64 0}135!4 = !{!"Simple C/C++ TBAA"}136