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1; RUN: llc -mtriple=hexagon < %s2; REQUIRES: asserts3 4; Test that the pipeliner doesn't assert when renaming a phi5; that looks like: a = PHI b, a6 7%s.0 = type { i32, ptr, [0 x i32], [0 x i32], [1 x i32] }8%s.1 = type { %s.2, %s.4, %s.5 }9%s.2 = type { %s.3 }10%s.3 = type { i32 }11%s.4 = type { i32 }12%s.5 = type { [0 x i32], [0 x ptr] }13 14@g0 = external global i32, align 415@g1 = external global %s.0, align 416@g2 = external global i32, align 417@g3 = external global i32, align 418@g4 = external global ptr, align 419 20define void @f0(ptr nocapture readonly %a0) #0 {21b0:22 %v0 = alloca [0 x i32], align 423 %v1 = load i32, ptr @g0, align 424 %v2 = load i32, ptr undef, align 425 %v3 = load ptr, ptr getelementptr inbounds (%s.0, ptr @g1, i32 0, i32 1), align 426 %v4 = load i32, ptr @g2, align 427 %v5 = sub i32 0, %v428 %v6 = getelementptr inbounds i32, ptr %v3, i32 %v529 %v7 = load i32, ptr undef, align 430 switch i32 %v7, label %b15 [31 i32 0, label %b132 i32 1, label %b233 ]34 35b1: ; preds = %b036 store i32 0, ptr @g3, align 437 br label %b238 39b2: ; preds = %b1, %b040 %v8 = icmp eq i32 %v1, 041 %v9 = icmp sgt i32 %v2, 042 %v11 = sdiv i32 %v2, 243 %v12 = add i32 %v11, -144 %v13 = getelementptr inbounds [0 x i32], ptr %v0, i32 0, i32 145 %v14 = getelementptr inbounds %s.1, ptr %a0, i32 0, i32 2, i32 1, i32 %v146 %v15 = sub i32 1, %v447 %v16 = getelementptr inbounds i32, ptr %v3, i32 %v1548 %v17 = sdiv i32 %v2, 449 %v18 = icmp slt i32 %v2, -350 %v19 = add i32 %v2, -151 %v20 = lshr i32 %v19, 252 %v21 = mul i32 %v20, 453 %v22 = add i32 %v21, 454 %v23 = add i32 %v11, -255 %v24 = add i32 %v17, 156 %v25 = select i1 %v18, i32 1, i32 %v2457 br label %b458 59b3: ; preds = %b1460 store i32 %v25, ptr @g3, align 461 br label %b462 63b4: ; preds = %b13, %b3, %b264 %v26 = phi i32 [ undef, %b2 ], [ %v42, %b3 ], [ %v42, %b13 ]65 %v27 = phi i32 [ undef, %b2 ], [ 0, %b3 ], [ 0, %b13 ]66 %v28 = phi i32 [ undef, %b2 ], [ %v30, %b3 ], [ %v30, %b13 ]67 %v29 = phi i32 [ undef, %b2 ], [ %v43, %b3 ], [ %v43, %b13 ]68 %v30 = phi i32 [ undef, %b2 ], [ undef, %b3 ], [ 0, %b13 ]69 br i1 %v8, label %b6, label %b570 71b5: ; preds = %b5, %b472 br label %b573 74b6: ; preds = %b475 br i1 %v9, label %b8, label %b776 77b7: ; preds = %b678 store i32 0, ptr @g3, align 479 br label %b1180 81b8: ; preds = %b682 br i1 undef, label %b9, label %b1183 84b9: ; preds = %b885 %v31 = load ptr, ptr @g4, align 486 br label %b1087 88b10: ; preds = %b10, %b989 %v32 = phi i32 [ %v22, %b9 ], [ %v39, %b10 ]90 %v33 = phi i32 [ %v29, %b9 ], [ %v38, %b10 ]91 %v34 = add nsw i32 %v32, %v2892 %v35 = shl i32 %v34, 193 %v36 = getelementptr inbounds i32, ptr %v31, i32 %v3594 %v37 = load i32, ptr %v36, align 495 %v38 = select i1 false, i32 0, i32 %v3396 %v39 = add nsw i32 %v32, 197 store i32 %v39, ptr @g3, align 498 %v40 = icmp slt i32 %v39, 099 br i1 %v40, label %b10, label %b11100 101b11: ; preds = %b10, %b8, %b7102 %v41 = phi i32 [ %v29, %b8 ], [ %v29, %b7 ], [ %v38, %b10 ]103 br i1 false, label %b12, label %b13104 105b12: ; preds = %b11106 br label %b13107 108b13: ; preds = %b12, %b11109 %v42 = load i32, ptr %v0, align 4110 %v43 = select i1 false, i32 %v41, i32 1111 br i1 %v18, label %b4, label %b14112 113b14: ; preds = %b14, %b13114 br i1 false, label %b14, label %b3115 116b15: ; preds = %b0117 ret void118}119 120attributes #0 = { nounwind "target-cpu"="hexagonv55" }121