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1; RUN: llc -mtriple=hexagon -mno-pairing -mno-compound < %s2; REQUIRES: asserts3 4; Test that the SWP doesn't assert when generating new phis. In this example, a5; phi references another phi and phi as well as the phi loop value are all6; defined in different stages.7; v3 = stage 28; v2 = phi(vb, v3) stage 19; v1 = phi(va, v2) stage 010 11; Function Attrs: nounwind12define void @f0() #0 {13b0:14 br label %b115 16b1: ; preds = %b1, %b017 br i1 undef, label %b2, label %b118 19b2: ; preds = %b120 br label %b321 22b3: ; preds = %b3, %b223 br i1 undef, label %b3, label %b424 25b4: ; preds = %b4, %b326 %v0 = phi i32 [ %v17, %b4 ], [ undef, %b3 ]27 %v1 = phi i64 [ %v13, %b4 ], [ undef, %b3 ]28 %v2 = phi i32 [ %v19, %b4 ], [ undef, %b3 ]29 %v3 = phi i32 [ %v4, %b4 ], [ undef, %b3 ]30 %v4 = phi i32 [ %v14, %b4 ], [ undef, %b3 ]31 %v5 = phi i32 [ %v18, %b4 ], [ undef, %b3 ]32 %v6 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v3, i32 %v3)33 %v7 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v0, i32 undef)34 %v8 = tail call i64 @llvm.hexagon.S2.valignib(i64 %v7, i64 undef, i32 2)35 %v9 = inttoptr i32 %v5 to ptr36 %v10 = load i16, ptr %v9, align 2, !tbaa !037 %v11 = sext i16 %v10 to i3238 %v12 = add nsw i32 %v5, -839 %v13 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v1, i64 %v6, i64 %v8)40 %v14 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 %v11, i32 %v0)41 %v15 = inttoptr i32 %v12 to ptr42 %v16 = load i16, ptr %v15, align 2, !tbaa !043 %v17 = sext i16 %v16 to i3244 %v18 = add nsw i32 %v5, -1645 %v19 = add nsw i32 %v2, 146 %v20 = icmp eq i32 %v19, 047 br i1 %v20, label %b5, label %b448 49b5: ; preds = %b450 %v21 = phi i64 [ %v13, %b4 ]51 unreachable52}53 54; Function Attrs: nounwind readnone55declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) #156 57; Function Attrs: nounwind readnone58declare i64 @llvm.hexagon.A2.combinew(i32, i32) #159 60; Function Attrs: nounwind readnone61declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #162 63; Function Attrs: nounwind readnone64declare i64 @llvm.hexagon.S2.valignib(i64, i64, i32) #165 66attributes #0 = { nounwind "target-cpu"="hexagonv60" }67attributes #1 = { nounwind readnone }68 69!0 = !{!1, !1, i64 0}70!1 = !{!"short", !2, i64 0}71!2 = !{!"omnipotent char", !3, i64 0}72!3 = !{!"Simple C/C++ TBAA"}73