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1; RUN: llc -mtriple=hexagon -enable-pipeliner < %s2; REQUIRES: asserts3 4; Make sure pipeliner handle physical registers (e.g., used in5; inline asm6 7@g0 = external global ptr, align 48 9; Function Attrs: nounwind10define i32 @f0(i32 %a0, ptr nocapture %a1) #0 {11b0:12 br i1 undef, label %b1, label %b213 14b1: ; preds = %b015 unreachable16 17b2: ; preds = %b018 br label %b319 20b3: ; preds = %b3, %b221 br i1 undef, label %b4, label %b322 23b4: ; preds = %b324 br label %b525 26b5: ; preds = %b5, %b427 %v0 = phi ptr [ inttoptr (i32 33554432 to ptr), %b4 ], [ %v4, %b5 ]28 %v1 = phi i32 [ 0, %b4 ], [ %v5, %b5 ]29 %v2 = ptrtoint ptr %v0 to i3230 tail call void asm sideeffect " r1 = $1\0A r0 = $0\0A memw(r0) = r1\0A dcfetch(r0)\0A", "r,r,~{r0},~{r1}"(i32 %v2, i32 %v1) #031 %v3 = load ptr, ptr @g0, align 432 %v4 = getelementptr inbounds i32, ptr %v3, i32 133 store ptr %v4, ptr @g0, align 434 %v5 = add nsw i32 %v1, 135 %v6 = icmp eq i32 %v5, 20036 br i1 %v6, label %b6, label %b537 38b6: ; preds = %b539 br label %b740 41b7: ; preds = %b7, %b642 br i1 undef, label %b8, label %b743 44b8: ; preds = %b745 ret i32 046}47 48attributes #0 = { nounwind "target-cpu"="hexagonv55" }49