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1; RUN: llc -mtriple=hexagon -enable-pipeliner < %s2; REQUIRES: asserts3 4; Test that the pipeliner doesn't ICE in the ScheduleDAG code because5; the latency values are not updated properly. The pipeliner should6; not change the latency of chain edges.7 8; Function Attrs: nounwind9define void @f0() #0 {10b0:11 %v0 = alloca [10 x i16], align 812 br label %b113 14b1: ; preds = %b1, %b015 %v1 = phi i32 [ %v7, %b1 ], [ undef, %b0 ]16 %v2 = add i32 %v1, -117 %v3 = getelementptr inbounds [10 x i16], ptr %v0, i32 0, i32 %v218 %v4 = add i32 %v1, -219 %v5 = getelementptr inbounds [10 x i16], ptr %v0, i32 0, i32 %v420 %v6 = load i16, ptr %v5, align 2, !tbaa !021 store i16 %v6, ptr %v3, align 2, !tbaa !022 %v7 = add i32 %v1, -423 %v8 = icmp sgt i32 %v7, 324 br i1 %v8, label %b1, label %b225 26b2: ; preds = %b2, %b127 br label %b228}29 30attributes #0 = { nounwind "target-cpu"="hexagonv55" }31 32!0 = !{!1, !1, i64 0}33!1 = !{!"short", !2, i64 0}34!2 = !{!"omnipotent char", !3, i64 0}35!3 = !{!"Simple C/C++ TBAA"}36