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1; RUN: llc -mtriple=hexagon < %s2; REQUIRES: asserts3 4; Function Attrs: nounwind5define void @f0(i32 %a0) #0 {6b0:7 %v0 = ashr i32 %a0, 18 br label %b19 10b1: ; preds = %b1, %b011 %v1 = phi i32 [ %v17, %b1 ], [ undef, %b0 ]12 %v2 = phi i32 [ %v19, %b1 ], [ 0, %b0 ]13 %v3 = phi i32 [ %v4, %b1 ], [ undef, %b0 ]14 %v4 = phi i32 [ %v14, %b1 ], [ undef, %b0 ]15 %v5 = phi i32 [ %v18, %b1 ], [ undef, %b0 ]16 %v6 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v1, i32 undef)17 %v7 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v3, i32 %v3)18 %v8 = tail call i64 @llvm.hexagon.S2.valignib(i64 %v6, i64 undef, i32 2)19 %v9 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 undef, i64 %v7, i64 %v8)20 %v10 = inttoptr i32 %v5 to ptr21 %v11 = load i16, ptr %v10, align 222 %v12 = sext i16 %v11 to i3223 %v13 = add nsw i32 %v5, -824 %v14 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 %v12, i32 %v1)25 %v15 = inttoptr i32 %v13 to ptr26 %v16 = load i16, ptr %v15, align 227 %v17 = sext i16 %v16 to i3228 %v18 = add nsw i32 %v5, -1629 %v19 = add nsw i32 %v2, 130 %v20 = icmp eq i32 %v19, %v031 br i1 %v20, label %b2, label %b132 33b2: ; preds = %b134 %v21 = phi i64 [ %v9, %b1 ]35 %v22 = trunc i64 %v21 to i3236 store i32 %v22, ptr undef, align 437 call void @llvm.trap()38 unreachable39}40 41; Function Attrs: nounwind readnone42declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) #143 44; Function Attrs: nounwind readnone45declare i64 @llvm.hexagon.A2.combinew(i32, i32) #146 47; Function Attrs: nounwind readnone48declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #149 50; Function Attrs: nounwind readnone51declare i64 @llvm.hexagon.S2.valignib(i64, i64, i32) #152 53; Function Attrs: noreturn nounwind54declare void @llvm.trap() #255 56attributes #0 = { nounwind "target-cpu"="hexagonv60" }57attributes #1 = { nounwind readnone }58attributes #2 = { noreturn nounwind }59