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1; RUN: llc -mtriple=hexagon -enable-pipeliner < %s2; REQUIRES: asserts3 4; Function Attrs: nounwind5define void @f0() #0 {6b0:7 br i1 undef, label %b1, label %b38 9b1: ; preds = %b010 br label %b211 12b2: ; preds = %b2, %b113 %v0 = phi i32 [ 0, %b1 ], [ %v9, %b2 ]14 %v1 = phi <16 x i32> [ undef, %b1 ], [ %v2, %b2 ]15 %v2 = phi <16 x i32> [ undef, %b1 ], [ %v4, %b2 ]16 %v3 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v2, <16 x i32> %v1, i32 62)17 %v4 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> undef, <16 x i32> zeroinitializer)18 %v5 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v4, <16 x i32> %v2, i32 2)19 %v6 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> undef, <16 x i32> %v3)20 %v7 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v6, <16 x i32> %v5)21 %v8 = tail call <16 x i32> @llvm.hexagon.V6.vabsh(<16 x i32> %v7)22 store <16 x i32> %v8, ptr undef, align 6423 %v9 = add nsw i32 %v0, 124 %v10 = icmp slt i32 %v9, undef25 br i1 %v10, label %b2, label %b326 27b3: ; preds = %b2, %b028 ret void29}30 31; Function Attrs: nounwind readnone32declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #133 34; Function Attrs: nounwind readnone35declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #136 37; Function Attrs: nounwind readnone38declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #139 40; Function Attrs: nounwind readnone41declare <16 x i32> @llvm.hexagon.V6.vabsh(<16 x i32>) #142 43attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }44attributes #1 = { nounwind readnone }45