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1; RUN: llc -mtriple=hexagon -O2 -simplifycfg-require-and-preserve-domtree=1 < %s2; REQUIRES: asserts3 4; Test that we generate the correct Phi names in the epilog when we need5; to reuse an existing Phi. This bug caused an assert in live variable6; analysis because the wrong virtual register was used.7; The bug occurs when a Phi references another Phi, and referent Phi8; value is used in multiple stages. When this occurs, the referring Phi9; can reuse one of the new values. We have code that deals with this in the10; kernel, but this case can occur in the epilog too.11 12; Function Attrs: nounwind readnone13declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #014 15; Function Attrs: nounwind readnone16declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #017 18; Function Attrs: nounwind readnone19declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #020 21; Function Attrs: nounwind readnone22declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #023 24; Function Attrs: nounwind readnone25declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #026 27; Function Attrs: nounwind readnone28declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #029 30; Function Attrs: nounwind readnone31declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #032 33; Function Attrs: nounwind readnone34declare <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32>, <16 x i32>, i32) #035 36; Function Attrs: nounwind readnone37declare <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32>, <16 x i32>) #038 39; Function Attrs: nounwind40define void @f0(ptr noalias nocapture readonly %a0, i32 %a1, i32 %a2) #1 {41b0:42 %v0 = mul nsw i32 %a1, 243 br i1 undef, label %b1, label %b544 45b1: ; preds = %b046 %v1 = getelementptr inbounds i8, ptr %a0, i32 %v047 %v2 = icmp sgt i32 %a2, 6448 %v3 = add i32 %v0, 6449 %v4 = add i32 %a1, 6450 %v5 = sub i32 64, %a151 %v6 = sub i32 64, %v052 br i1 %v2, label %b2, label %b453 54b2: ; preds = %b155 %v7 = getelementptr inbounds i8, ptr %v1, i32 %v356 %v8 = getelementptr inbounds i8, ptr %v1, i32 %v457 %v9 = getelementptr inbounds i8, ptr %v1, i32 6458 %v10 = getelementptr inbounds i8, ptr %v1, i32 %v559 %v11 = getelementptr inbounds i8, ptr %v1, i32 %v660 br label %b361 62b3: ; preds = %b3, %b263 %v17 = phi ptr [ null, %b2 ], [ %v52, %b3 ]64 %v18 = phi ptr [ %v7, %b2 ], [ %v34, %b3 ]65 %v19 = phi ptr [ %v8, %b2 ], [ %v32, %b3 ]66 %v20 = phi ptr [ %v9, %b2 ], [ %v30, %b3 ]67 %v21 = phi ptr [ %v10, %b2 ], [ %v28, %b3 ]68 %v22 = phi ptr [ %v11, %b2 ], [ %v26, %b3 ]69 %v23 = phi <32 x i32> [ undef, %b2 ], [ %v37, %b3 ]70 %v24 = phi <32 x i32> [ zeroinitializer, %b2 ], [ %v23, %b3 ]71 %v25 = phi i32 [ %a2, %b2 ], [ %v53, %b3 ]72 %v26 = getelementptr inbounds <16 x i32>, ptr %v22, i32 173 %v27 = load <16 x i32>, ptr %v22, align 6474 %v28 = getelementptr inbounds <16 x i32>, ptr %v21, i32 175 %v29 = load <16 x i32>, ptr %v21, align 6476 %v30 = getelementptr inbounds <16 x i32>, ptr %v20, i32 177 %v31 = load <16 x i32>, ptr %v20, align 6478 %v32 = getelementptr inbounds <16 x i32>, ptr %v19, i32 179 %v33 = load <16 x i32>, ptr %v19, align 6480 %v34 = getelementptr inbounds <16 x i32>, ptr %v18, i32 181 %v35 = load <16 x i32>, ptr %v18, align 6482 %v36 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v33, <16 x i32> %v29) #383 %v37 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> undef, <32 x i32> %v36, i32 67372036) #384 %v38 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v23) #385 %v39 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v24) #386 %v40 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v38, <16 x i32> %v39, i32 2) #387 %v41 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v37) #388 %v42 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v41, <16 x i32> %v38, i32 2) #389 %v43 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v37) #390 %v44 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v43, <16 x i32> undef, i32 2) #391 %v45 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v40, <16 x i32> %v42) #392 %v46 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32> %v45, <16 x i32> %v38, i32 101058054) #393 %v47 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32> %v46, <16 x i32> zeroinitializer, i32 67372036) #394 %v48 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> undef, <16 x i32> %v44) #395 %v49 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32> %v48, <16 x i32> undef, i32 101058054) #396 %v50 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32> %v49, <16 x i32> zeroinitializer, i32 67372036) #397 %v51 = tail call <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32> %v50, <16 x i32> %v47) #398 %v52 = getelementptr inbounds <16 x i32>, ptr %v17, i32 199 store <16 x i32> %v51, ptr %v17, align 64100 %v53 = add nsw i32 %v25, -64101 %v54 = icmp sgt i32 %v53, 64102 br i1 %v54, label %b3, label %b4103 104b4: ; preds = %b3, %b1105 unreachable106 107b5: ; preds = %b0108 ret void109}110 111; Function Attrs: nounwind112define void @f1(i32 %a0, ptr %a1) #1 {113b0:114 %v0 = ptrtoint ptr %a1 to i32115 %v1 = ashr i32 %a0, 1116 %v2 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 undef, i32 undef)117 br i1 undef, label %b1, label %b2118 119b1: ; preds = %b1, %b0120 br i1 undef, label %b1, label %b2121 122b2: ; preds = %b2, %b1, %b0123 %v3 = phi i64 [ %v11, %b2 ], [ undef, %b0 ], [ undef, %b1 ]124 %v4 = phi i32 [ %v12, %b2 ], [ 0, %b0 ], [ undef, %b1 ]125 %v5 = phi i32 [ %v6, %b2 ], [ %v2, %b0 ], [ undef, %b1 ]126 %v6 = phi i32 [ %v10, %b2 ], [ undef, %b0 ], [ undef, %b1 ]127 %v7 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 undef, i64 %v3, i64 undef)128 %v8 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v5, i32 %v5)129 %v9 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 undef, i64 %v8, i64 undef)130 %v10 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 0, i32 undef)131 %v11 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v10, i32 %v6)132 %v12 = add nsw i32 %v4, 1133 %v13 = icmp eq i32 %v12, %v1134 br i1 %v13, label %b3, label %b2135 136b3: ; preds = %b2137 %v14 = phi i64 [ %v9, %b2 ]138 %v15 = phi i64 [ %v7, %b2 ]139 %v16 = trunc i64 %v14 to i32140 %v17 = trunc i64 %v15 to i32141 %v18 = inttoptr i32 %v0 to ptr142 store i32 %v17, ptr %v18, align 4143 store i32 %v16, ptr undef, align 4144 call void @llvm.trap()145 unreachable146}147 148; Function Attrs: nounwind readnone149declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) #0150 151; Function Attrs: nounwind readnone152declare i64 @llvm.hexagon.A2.combinew(i32, i32) #0153 154; Function Attrs: nounwind readnone155declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #0156 157; Function Attrs: noreturn nounwind158declare void @llvm.trap() #2159 160attributes #0 = { nounwind readnone }161attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }162attributes #2 = { noreturn nounwind }163attributes #3 = { nounwind }164