179 lines · plain
1; RUN: llc -mtriple=hexagon -O2 < %s -pipeliner-experimental-cg=true -verify-machineinstrs | FileCheck %s2 3; We do not pipeline sigma yet, but the non-pipelined version4; with good scheduling is pretty fast. The compiler generates5; 18 packets, and the assembly version is 16.6 7; CHECK: loop0(.LBB0_[[LOOP:.]],8; CHECK: .LBB0_[[LOOP]]:9; CHECK-COUNT-17: }10; CHECK: }{{[ \t]*}}:endloop11 12@g0 = external constant [10 x i16], align 12813 14declare i32 @llvm.hexagon.S2.vsplatrb(i32) #015declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #016declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #017declare <16 x i32> @llvm.hexagon.V6.vd0() #018declare <32 x i32> @llvm.hexagon.V6.vsububh(<16 x i32>, <16 x i32>) #019declare <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32>, <16 x i32>) #020declare <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32>, <16 x i32>) #021declare <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1>, <16 x i32>, <16 x i32>) #022declare <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1>, <16 x i32>, <16 x i32>) #023declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #024declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #025declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #026declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #027declare <32 x i32> @llvm.hexagon.V6.vlutvwh(<16 x i32>, <16 x i32>, i32) #028declare <16 x i32> @llvm.hexagon.V6.vmpyhvsrs(<16 x i32>, <16 x i32>) #029declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #030declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #031declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #032 33define void @f0(ptr nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, i8 zeroext %a4, ptr nocapture %a5) #1 {34b0:35 %v0 = add nsw i32 %a3, -136 %v1 = icmp sgt i32 %v0, 137 br i1 %v1, label %b1, label %b838 39b1: ; preds = %b040 %v2 = mul i32 %a1, 241 %v3 = load <16 x i32>, ptr @g0, align 12842 %v4 = tail call <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32> %v3) #243 %v5 = zext i8 %a4 to i3244 %v6 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %v5) #245 %v7 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v6) #246 %v8 = tail call <16 x i32> @llvm.hexagon.V6.vd0() #247 %v9 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 16843009) #248 %v10 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 33686018) #249 %v11 = icmp sgt i32 %a2, 6450 %v12 = add i32 %a1, 6451 %v13 = add i32 %v12, %a152 %v14 = icmp sgt i32 %a2, 053 %v15 = add i32 %a3, -254 %v17 = load <16 x i32>, ptr %a0, align 6455 br label %b256 57b2: ; preds = %b7, %b158 %v18 = phi <16 x i32> [ %v17, %b1 ], [ %v28, %b7 ]59 %v19 = phi ptr [ %a0, %b1 ], [ %v23, %b7 ]60 %v20 = phi ptr [ %a5, %b1 ], [ %v22, %b7 ]61 %v21 = phi i32 [ 1, %b1 ], [ %v118, %b7 ]62 %v22 = getelementptr inbounds i8, ptr %v20, i32 %a163 %v23 = getelementptr inbounds i8, ptr %v19, i32 %a164 %v25 = getelementptr inbounds i8, ptr %v19, i32 %v265 %v28 = load <16 x i32>, ptr %v23, align 6466 %v29 = load <16 x i32>, ptr %v25, align 6467 br i1 %v11, label %b3, label %b468 69b3: ; preds = %b270 %v30 = getelementptr inbounds i8, ptr %v19, i32 6471 %v31 = getelementptr inbounds i8, ptr %v19, i32 %v1272 %v33 = getelementptr inbounds i8, ptr %v19, i32 %v1373 br label %b574 75b4: ; preds = %b276 br i1 %v14, label %b5, label %b777 78b5: ; preds = %b4, %b379 %v35 = phi ptr [ %v25, %b4 ], [ %v33, %b3 ]80 %v36 = phi ptr [ %v23, %b4 ], [ %v31, %b3 ]81 %v37 = phi ptr [ %v19, %b4 ], [ %v30, %b3 ]82 br label %b683 84b6: ; preds = %b6, %b585 %v39 = phi ptr [ %v108, %b6 ], [ %v22, %b5 ]86 %v40 = phi ptr [ %v115, %b6 ], [ %v35, %b5 ]87 %v41 = phi ptr [ %v114, %b6 ], [ %v36, %b5 ]88 %v42 = phi ptr [ %v113, %b6 ], [ %v37, %b5 ]89 %v43 = phi i32 [ %v116, %b6 ], [ %a2, %b5 ]90 %v44 = phi <16 x i32> [ %v45, %b6 ], [ %v8, %b5 ]91 %v45 = phi <16 x i32> [ %v50, %b6 ], [ %v18, %b5 ]92 %v46 = phi <16 x i32> [ %v47, %b6 ], [ %v8, %b5 ]93 %v47 = phi <16 x i32> [ %v51, %b6 ], [ %v28, %b5 ]94 %v48 = phi <16 x i32> [ %v49, %b6 ], [ %v8, %b5 ]95 %v49 = phi <16 x i32> [ %v52, %b6 ], [ %v29, %b5 ]96 %v50 = load <16 x i32>, ptr %v42, align 6497 %v51 = load <16 x i32>, ptr %v41, align 6498 %v52 = load <16 x i32>, ptr %v40, align 6499 %v53 = tail call <32 x i32> @llvm.hexagon.V6.vsububh(<16 x i32> %v8, <16 x i32> %v47) #2100 %v54 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v45, <16 x i32> %v47) #2101 %v55 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v49, <16 x i32> %v47) #2102 %v56 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v54, <16 x i32> %v7) #2103 %v57 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v55, <16 x i32> %v7) #2104 %v58 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v56, <16 x i32> %v9, <16 x i32> %v10) #2105 %v59 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v57, <16 x i32> %v58, <16 x i32> %v9) #2106 %v60 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v56, <16 x i32> %v8, <16 x i32> %v45) #2107 %v61 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v57, <16 x i32> %v8, <16 x i32> %v49) #2108 %v62 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v61, <16 x i32> %v60) #2109 %v63 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v53, <32 x i32> %v62, i32 -1) #2110 %v64 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v45, <16 x i32> %v44, i32 1) #2111 %v65 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v49, <16 x i32> %v48, i32 1) #2112 %v66 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v64, <16 x i32> %v47) #2113 %v67 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v65, <16 x i32> %v47) #2114 %v68 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v66, <16 x i32> %v7) #2115 %v69 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v67, <16 x i32> %v7) #2116 %v70 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v68, <16 x i32> %v59, <16 x i32> %v9) #2117 %v71 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v69, <16 x i32> %v70, <16 x i32> %v9) #2118 %v72 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v68, <16 x i32> %v8, <16 x i32> %v64) #2119 %v73 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v69, <16 x i32> %v8, <16 x i32> %v65) #2120 %v74 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v73, <16 x i32> %v72) #2121 %v75 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v63, <32 x i32> %v74, i32 -1) #2122 %v76 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v50, <16 x i32> %v45, i32 1) #2123 %v77 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v52, <16 x i32> %v49, i32 1) #2124 %v78 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v76, <16 x i32> %v47) #2125 %v79 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v77, <16 x i32> %v47) #2126 %v80 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v78, <16 x i32> %v7) #2127 %v81 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v79, <16 x i32> %v7) #2128 %v82 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v80, <16 x i32> %v71, <16 x i32> %v9) #2129 %v83 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v81, <16 x i32> %v82, <16 x i32> %v9) #2130 %v84 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v80, <16 x i32> %v8, <16 x i32> %v76) #2131 %v85 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v81, <16 x i32> %v8, <16 x i32> %v77) #2132 %v86 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v85, <16 x i32> %v84) #2133 %v87 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v75, <32 x i32> %v86, i32 -1) #2134 %v88 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v47, <16 x i32> %v46, i32 1) #2135 %v89 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v51, <16 x i32> %v47, i32 1) #2136 %v90 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v88, <16 x i32> %v47) #2137 %v91 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v89, <16 x i32> %v47) #2138 %v92 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v90, <16 x i32> %v7) #2139 %v93 = tail call <64 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v91, <16 x i32> %v7) #2140 %v94 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v92, <16 x i32> %v83, <16 x i32> %v9) #2141 %v95 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v93, <16 x i32> %v94, <16 x i32> %v9) #2142 %v96 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v92, <16 x i32> %v8, <16 x i32> %v88) #2143 %v97 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v93, <16 x i32> %v8, <16 x i32> %v89) #2144 %v98 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v97, <16 x i32> %v96) #2145 %v99 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %v87, <32 x i32> %v98, i32 -1) #2146 %v100 = tail call <32 x i32> @llvm.hexagon.V6.vlutvwh(<16 x i32> %v95, <16 x i32> %v4, i32 0) #2147 %v101 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v99) #2148 %v102 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v100) #2149 %v103 = tail call <16 x i32> @llvm.hexagon.V6.vmpyhvsrs(<16 x i32> %v101, <16 x i32> %v102) #2150 %v104 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v99) #2151 %v105 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v100) #2152 %v106 = tail call <16 x i32> @llvm.hexagon.V6.vmpyhvsrs(<16 x i32> %v104, <16 x i32> %v105) #2153 %v107 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v106, <16 x i32> %v103) #2154 %v108 = getelementptr inbounds <16 x i32>, ptr %v39, i32 1155 store <16 x i32> %v107, ptr %v39, align 64156 %v109 = icmp sgt i32 %v43, 128157 %v110 = getelementptr inbounds <16 x i32>, ptr %v42, i32 1158 %v111 = getelementptr inbounds <16 x i32>, ptr %v41, i32 1159 %v112 = getelementptr inbounds <16 x i32>, ptr %v40, i32 1160 %v113 = select i1 %v109, ptr %v110, ptr %v42161 %v114 = select i1 %v109, ptr %v111, ptr %v41162 %v115 = select i1 %v109, ptr %v112, ptr %v40163 %v116 = add nsw i32 %v43, -64164 %v117 = icmp sgt i32 %v43, 64165 br i1 %v117, label %b6, label %b7166 167b7: ; preds = %b6, %b4168 %v118 = add nuw nsw i32 %v21, 1169 %v119 = icmp eq i32 %v21, %v15170 br i1 %v119, label %b8, label %b2171 172b8: ; preds = %b7, %b0173 ret void174}175 176attributes #0 = { nounwind readnone }177attributes #1 = { nounwind "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" }178attributes #2 = { nounwind }179