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1; RUN: llc -mtriple=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s2; RUN: llc -mtriple=hexagon -mcpu=hexagonv60 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s --check-prefix=CHECKV603 4; Simple vector total.5; CHECK: loop0(.LBB0_[[LOOP:.]],6; CHECK: .LBB0_[[LOOP]]:7; CHECK: add(r{{[0-9]+}},r{{[0-9]+}})8; CHECK-NEXT: memw(r{{[0-9]+}}++#4)9; CHECK-NEXT: endloop010 11; V60 does not pipeline due to latencies.12; CHECKV60: memw(r{{[0-9]+}}++#4)13; CHECKV60: add(r{{[0-9]+}},r{{[0-9]+}})14 15define i32 @f0(ptr %a0, i32 %a1) {16b0:17 br label %b118 19b1: ; preds = %b1, %b020 %v0 = phi i32 [ 0, %b0 ], [ %v4, %b1 ]21 %v1 = phi ptr [ %a0, %b0 ], [ %v7, %b1 ]22 %v2 = phi i32 [ 0, %b0 ], [ %v5, %b1 ]23 %v3 = load i32, ptr %v1, align 424 %v4 = add nsw i32 %v3, %v025 %v5 = add nsw i32 %v2, 126 %v6 = icmp eq i32 %v5, 1000027 %v7 = getelementptr i32, ptr %v1, i32 128 br i1 %v6, label %b2, label %b129 30b2: ; preds = %b131 ret i32 %v432}33