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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -o -| FileCheck %s3 4--- |5 define void @test_swp_ws_live_intervals(i32 %.pre) {6 entry:7 %cgep9 = bitcast ptr null to ptr8 br label %for.body1479 10 for.body147: ; preds = %for.body170, %entry11 %add11.i526 = or i32 %.pre, 112 br label %for.body15813 14 for.body158: ; preds = %for.body158, %for.body14715 %lsr.iv = phi i32 [ %lsr.iv.next, %for.body158 ], [ -1, %for.body147 ]16 %add11.i536602603 = phi i32 [ %add11.i526, %for.body147 ], [ 0, %for.body158 ]17 %and8.i534 = and i32 %add11.i536602603, 118 %cgep7 = getelementptr [64 x i32], ptr %cgep9, i32 0, i32 %and8.i53419 store i32 0, ptr %cgep7, align 420 %lsr.iv.next = add nsw i32 %lsr.iv, 121 %cmp157.3 = icmp ult i32 %lsr.iv.next, 51022 br i1 %cmp157.3, label %for.body158, label %for.body17023 24 for.body170: ; preds = %for.body170, %for.body15825 %lsr.iv3 = phi ptr [ %cgep6, %for.body170 ], [ inttoptr (i32 4 to ptr), %for.body158 ]26 %lsr.iv1 = phi i32 [ %lsr.iv.next2, %for.body170 ], [ -1, %for.body158 ]27 %add11.i556606607 = phi i32 [ 0, %for.body170 ], [ 1, %for.body158 ]28 %cgep5 = getelementptr i8, ptr %lsr.iv3, i32 -429 store i32 0, ptr %cgep5, align 830 %sub.i547.1 = add i32 %add11.i556606607, 131 %and.i548.1 = and i32 %sub.i547.1, 132 %cgep8 = getelementptr [64 x i32], ptr %cgep9, i32 0, i32 %and.i548.133 %0 = load i32, ptr %cgep8, align 434 store i32 %0, ptr %lsr.iv3, align 435 %lsr.iv.next2 = add nsw i32 %lsr.iv1, 136 %cmp169.1 = icmp ult i32 %lsr.iv.next2, 25437 %cgep6 = getelementptr i8, ptr %lsr.iv3, i32 238 br i1 %cmp169.1, label %for.body170, label %for.body14739 }40 41...42---43name: test_swp_ws_live_intervals44tracksRegLiveness: true45body: |46 ; CHECK-LABEL: name: test_swp_ws_live_intervals47 ; CHECK: bb.0.entry:48 ; CHECK-NEXT: successors: %bb.1(0x80000000)49 ; CHECK-NEXT: liveins: $r050 ; CHECK-NEXT: {{ $}}51 ; CHECK-NEXT: [[COPY:%[0-9]+]]:intregs = COPY $r052 ; CHECK-NEXT: [[S2_setbit_i:%[0-9]+]]:intregs = S2_setbit_i [[COPY]], 053 ; CHECK-NEXT: {{ $}}54 ; CHECK-NEXT: bb.1:55 ; CHECK-NEXT: successors: %bb.5(0x80000000)56 ; CHECK-NEXT: {{ $}}57 ; CHECK-NEXT: bb.5:58 ; CHECK-NEXT: successors: %bb.6(0x80000000)59 ; CHECK-NEXT: {{ $}}60 ; CHECK-NEXT: [[A2_andir:%[0-9]+]]:intregs = A2_andir [[S2_setbit_i]], 161 ; CHECK-NEXT: [[S2_asl_i_r:%[0-9]+]]:intregs = S2_asl_i_r [[A2_andir]], 262 ; CHECK-NEXT: [[A2_tfrsi:%[0-9]+]]:intregs = A2_tfrsi 163 ; CHECK-NEXT: [[A2_tfrsi1:%[0-9]+]]:intregs = A2_tfrsi 464 ; CHECK-NEXT: [[A2_tfrsi2:%[0-9]+]]:intregs = A2_tfrsi 065 ; CHECK-NEXT: J2_loop0i %bb.6, 510, implicit-def $lc0, implicit-def $sa0, implicit-def $usr66 ; CHECK-NEXT: J2_jump %bb.6, implicit-def $pc67 ; CHECK-NEXT: {{ $}}68 ; CHECK-NEXT: bb.6:69 ; CHECK-NEXT: successors: %bb.6(0x7c000000), %bb.7(0x04000000)70 ; CHECK-NEXT: {{ $}}71 ; CHECK-NEXT: [[PHI:%[0-9]+]]:intregs = PHI [[A2_tfrsi2]], %bb.5, %24, %bb.672 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:intregs = PHI [[S2_asl_i_r]], %bb.5, %23, %bb.673 ; CHECK-NEXT: S4_storeiri_io [[PHI1]], 0, 0 :: (store (s32) into %ir.cgep7)74 ; CHECK-NEXT: [[A2_andir1:%[0-9]+]]:intregs = A2_andir [[PHI]], 175 ; CHECK-NEXT: [[A2_tfrsi3:%[0-9]+]]:intregs = A2_tfrsi 176 ; CHECK-NEXT: [[A2_tfrsi4:%[0-9]+]]:intregs = A2_tfrsi 477 ; CHECK-NEXT: [[S2_asl_i_r1:%[0-9]+]]:intregs = S2_asl_i_r [[A2_andir1]], 278 ; CHECK-NEXT: [[A2_tfrsi5:%[0-9]+]]:intregs = A2_tfrsi 079 ; CHECK-NEXT: ENDLOOP0 %bb.6, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc080 ; CHECK-NEXT: J2_jump %bb.7, implicit-def $pc81 ; CHECK-NEXT: {{ $}}82 ; CHECK-NEXT: bb.7:83 ; CHECK-NEXT: successors: %bb.3(0x80000000)84 ; CHECK-NEXT: {{ $}}85 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:intregs = PHI [[S2_asl_i_r1]], %bb.686 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:intregs = PHI [[A2_tfrsi3]], %bb.687 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:intregs = PHI [[A2_tfrsi4]], %bb.688 ; CHECK-NEXT: S4_storeiri_io [[PHI2]], 0, 0 :: (store unknown-size into %ir.cgep7, align 4)89 ; CHECK-NEXT: J2_jump %bb.3, implicit-def $pc90 ; CHECK-NEXT: {{ $}}91 ; CHECK-NEXT: bb.3:92 ; CHECK-NEXT: successors: %bb.4(0x80000000)93 ; CHECK-NEXT: {{ $}}94 ; CHECK-NEXT: J2_loop0i %bb.4, 255, implicit-def $lc0, implicit-def $sa0, implicit-def $usr95 ; CHECK-NEXT: J2_jump %bb.4, implicit-def $pc96 ; CHECK-NEXT: {{ $}}97 ; CHECK-NEXT: bb.4:98 ; CHECK-NEXT: successors: %bb.4(0x7c000000), %bb.1(0x04000000)99 ; CHECK-NEXT: {{ $}}100 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:intregs = PHI [[PHI4]], %bb.3, %9, %bb.4101 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:intregs = PHI [[PHI3]], %bb.3, %11, %bb.4102 ; CHECK-NEXT: [[A2_tfrsi6:%[0-9]+]]:intregs = A2_tfrsi 0103 ; CHECK-NEXT: S2_storeri_io [[PHI5]], -4, [[A2_tfrsi6]] :: (store (s32) into %ir.cgep5, align 8)104 ; CHECK-NEXT: [[A2_addi:%[0-9]+]]:intregs = A2_addi [[PHI6]], 1105 ; CHECK-NEXT: [[S2_insert:%[0-9]+]]:intregs = S2_insert [[PHI2]], [[A2_addi]], 1, 2106 ; CHECK-NEXT: [[L2_loadri_io:%[0-9]+]]:intregs = L2_loadri_io [[S2_insert]], 0 :: (load (s32) from %ir.cgep8)107 ; CHECK-NEXT: S2_storeri_io [[PHI5]], 0, [[L2_loadri_io]] :: (store (s32) into %ir.lsr.iv3)108 ; CHECK-NEXT: [[A2_addi1:%[0-9]+]]:intregs = A2_addi [[PHI5]], 2109 ; CHECK-NEXT: ENDLOOP0 %bb.4, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0110 ; CHECK-NEXT: J2_jump %bb.1, implicit-def dead $pc111 bb.0.entry:112 successors: %bb.1(0x80000000)113 liveins: $r0114 115 %0:intregs = COPY $r0116 %1:intregs = S2_setbit_i %0, 0117 118 bb.1:119 successors: %bb.2(0x80000000)120 121 J2_loop0i %bb.2, 511, implicit-def $lc0, implicit-def $sa0, implicit-def $usr122 123 bb.2:124 successors: %bb.2(0x7c000000), %bb.3(0x04000000)125 126 %2:intregs = PHI %1, %bb.1, %3, %bb.2127 %4:intregs = A2_andir %2, 1128 %5:intregs = S2_asl_i_r %4, 2129 S4_storeiri_io %5, 0, 0 :: (store (s32) into %ir.cgep7)130 %6:intregs = A2_tfrsi 1131 %7:intregs = A2_tfrsi 4132 %3:intregs = A2_tfrsi 0133 ENDLOOP0 %bb.2, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0134 J2_jump %bb.3, implicit-def dead $pc135 136 bb.3:137 successors: %bb.4(0x80000000)138 139 J2_loop0i %bb.4, 255, implicit-def $lc0, implicit-def $sa0, implicit-def $usr140 J2_jump %bb.4, implicit-def $pc141 142 bb.4:143 successors: %bb.4(0x7c000000), %bb.1(0x04000000)144 145 %8:intregs = PHI %7, %bb.3, %9, %bb.4146 %10:intregs = PHI %6, %bb.3, %11, %bb.4147 %11:intregs = A2_tfrsi 0148 S2_storeri_io %8, -4, %11 :: (store (s32) into %ir.cgep5, align 8)149 %12:intregs = A2_addi %10, 1150 %13:intregs = S2_insert %5, %12, 1, 2151 %14:intregs = L2_loadri_io %13, 0 :: (load (s32) from %ir.cgep8)152 S2_storeri_io %8, 0, %14 :: (store (s32) into %ir.lsr.iv3)153 %9:intregs = A2_addi %8, 2154 ENDLOOP0 %bb.4, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0155 J2_jump %bb.1, implicit-def dead $pc156 157...158