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1# REQUIRES: asserts2# 3# RUN: llc --mtriple=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \4# RUN: -window-sched=force -filetype=null -window-search-num=100 \5# RUN: -window-search-ratio=100 -window-diff-limit=0 -verify-machineinstrs \6# RUN: 2>&1 | FileCheck %s7 8# The bug was reported at https://github.com/llvm/llvm-project/pull/99454. 9# It is caused by the corruption of live intervals in certain scenarios.10#11# We check the newly generated MBBs after successful scheduling here.12# CHECK: Best window offset is {{[0-9]+}} and Best II is {{[0-9]+}}.13# CHECK: prolog:14# CHECK: bb.5:15# CHECK: New block16# CHECK: bb.6:17# CHECK: epilog:18# CHECK: bb.7:19# CHECK: Best window offset is {{[0-9]+}} and Best II is {{[0-9]+}}.20# CHECK: prolog:21# CHECK: bb.8:22# CHECK: New block23# CHECK: bb.9:24# CHECK: epilog:25# CHECK: bb.10:26 27--- |28 target triple = "hexagon"29 30 @_dp_ctrl_calc_tu_temp2_fp = global i64 031 @_dp_ctrl_calc_tu_temp1_fp = global i32 032 @dp_panel_update_tu_timings___trans_tmp_5 = global i64 033 @_dp_ctrl_calc_tu___trans_tmp_8 = global i64 034 35 declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)36 declare i8 @div64_u64_rem(i32, ptr)37 declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)38 39 define void @dp_ctrl_calc_tu_parameters() {40 if.end.i:41 %rem.i11.i = alloca i64, align 842 %rem.i.i = alloca i64, align 843 call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %rem.i11.i)44 %call.i.i = call i8 @div64_u64_rem(i32 0, ptr nonnull %rem.i11.i)45 %conv1.i.i = zext i8 %call.i.i to i6446 %rem.promoted.i.i = load i64, ptr %rem.i11.i, align 847 br label %do.body.i.i48 49 do.body.i.i:50 %lsr.iv1 = phi i32 [ %lsr.iv.next2, %do.body.i.i ], [ -32, %if.end.i ]51 %sub9.i.i = phi i64 [ %rem.promoted.i.i, %if.end.i ], [ %sub8.i.i.7, %do.body.i.i ]52 %res_abs.0.i.i = phi i64 [ %conv1.i.i, %if.end.i ], [ %res_abs.1.i.i.7, %do.body.i.i ]53 %cmp.not.i.i = icmp ne i64 %sub9.i.i, 054 %sub.i.neg.i = sext i1 %cmp.not.i.i to i6455 %sub8.i.i = add i64 %sub9.i.i, %sub.i.neg.i56 %0 = shl i64 %res_abs.0.i.i, 257 %1 = select i1 %cmp.not.i.i, i64 2, i64 058 %shl.i.i.5 = or disjoint i64 %0, %159 %cmp.not.i.i.5 = icmp ne i64 %sub8.i.i, 060 %sub.i.neg.i.5 = sext i1 %cmp.not.i.i.5 to i6461 %sub8.i.i.5 = add i64 %sub8.i.i, %sub.i.neg.i.562 %or.i.i.5 = zext i1 %cmp.not.i.i.5 to i6463 %res_abs.1.i.i.5 = or disjoint i64 %shl.i.i.5, %or.i.i.564 %cmp.not.i.i.6 = icmp ne i64 %sub8.i.i.5, 065 %sub.i.neg.i.6 = sext i1 %cmp.not.i.i.6 to i6466 %sub8.i.i.6 = add i64 %sub8.i.i.5, %sub.i.neg.i.667 %2 = shl i64 %res_abs.1.i.i.5, 268 %3 = select i1 %cmp.not.i.i.6, i64 2, i64 069 %shl.i.i.7 = or disjoint i64 %2, %370 %cmp.not.i.i.7 = icmp ne i64 %sub8.i.i.6, 071 %sub.i.neg.i.7 = sext i1 %cmp.not.i.i.7 to i6472 %sub8.i.i.7 = add i64 %sub8.i.i.6, %sub.i.neg.i.773 %or.i.i.7 = zext i1 %cmp.not.i.i.7 to i6474 %res_abs.1.i.i.7 = or disjoint i64 %shl.i.i.7, %or.i.i.775 %lsr.iv.next2 = add nsw i32 %lsr.iv1, 876 %tobool.not.i.i.7 = icmp eq i32 %lsr.iv.next2, 077 br i1 %tobool.not.i.i.7, label %fec_check.i, label %do.body.i.i78 79 fec_check.i:80 call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %rem.i11.i)81 store i64 %res_abs.1.i.i.7, ptr @_dp_ctrl_calc_tu_temp2_fp, align 882 call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %rem.i11.i)83 %call.i12.i = call i8 @div64_u64_rem(i32 0, ptr nonnull %rem.i11.i)84 %conv1.i13.i = zext i8 %call.i12.i to i6485 %rem.promoted.i14.i = load i64, ptr %rem.i11.i, align 886 br label %do.body.i15.i87 88 do.body.i15.i:89 %lsr.iv = phi i32 [ %lsr.iv.next, %do.body.i15.i ], [ -32, %fec_check.i ]90 %sub9.i16.i = phi i64 [ %rem.promoted.i14.i, %fec_check.i ], [ %sub8.i22.i.7, %do.body.i15.i ]91 %res_abs.0.i17.i = phi i64 [ %conv1.i13.i, %fec_check.i ], [ %res_abs.1.i24.i.7, %do.body.i15.i ]92 %cmp.not.i20.i = icmp ugt i64 %sub9.i16.i, 99993 %sub.i21.neg.i = select i1 %cmp.not.i20.i, i64 -1000, i64 094 %sub8.i22.i = add i64 %sub.i21.neg.i, %sub9.i16.i95 %4 = shl i64 %res_abs.0.i17.i, 296 %5 = select i1 %cmp.not.i20.i, i64 2, i64 097 %shl.i19.i.7 = or disjoint i64 %4, %598 %cmp.not.i20.i.7 = icmp ugt i64 %sub8.i22.i, 99999 %sub.i21.neg.i.7 = select i1 %cmp.not.i20.i.7, i64 -1000, i64 0100 %sub8.i22.i.7 = add i64 %sub.i21.neg.i.7, %sub8.i22.i101 %or.i23.i.7 = zext i1 %cmp.not.i20.i.7 to i64102 %res_abs.1.i24.i.7 = or disjoint i64 %shl.i19.i.7, %or.i23.i.7103 %lsr.iv.next = add nsw i32 %lsr.iv, 8104 %tobool.not.i26.i.7 = icmp eq i32 %lsr.iv.next, 0105 br i1 %tobool.not.i26.i.7, label %_dp_ctrl_calc_tu.exit, label %do.body.i15.i106 107 _dp_ctrl_calc_tu.exit:108 call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %rem.i11.i)109 %conv.i = trunc i64 %res_abs.1.i24.i.7 to i32110 store i32 %conv.i, ptr @_dp_ctrl_calc_tu_temp1_fp, align 4111 %conv5.i = and i64 %res_abs.1.i24.i.7, 4294967295112 store i64 %conv5.i, ptr @dp_panel_update_tu_timings___trans_tmp_5, align 8113 store i64 %res_abs.1.i.i.7, ptr @_dp_ctrl_calc_tu___trans_tmp_8, align 8114 ret void115 }116 117...118---119name: dp_ctrl_calc_tu_parameters120tracksRegLiveness: true121stack:122 - { id: 0, name: rem.i11.i, type: default, offset: 0, size: 8, alignment: 8}123body: |124 bb.0:125 successors: %bb.1(0x80000000)126 127 %0:intregs = A2_tfrsi 0128 %1:intregs = PS_fi %stack.0.rem.i11.i, 0129 %2:intregs = A2_tfrsi 0130 %3:doubleregs = A4_combineir 0, %2131 %4:doubleregs = L2_loadrd_io %stack.0.rem.i11.i, 0132 %5:doubleregs = A2_tfrpi 0133 J2_loop0i %bb.1, 4, implicit-def $lc0, implicit-def $sa0, implicit-def $usr134 135 bb.1 (machine-block-address-taken):136 successors: %bb.2(0x04000000), %bb.1(0x7c000000)137 138 %6:doubleregs = PHI %4, %bb.0, %7, %bb.1139 %8:doubleregs = PHI %3, %bb.0, %9, %bb.1140 %10:predregs = C2_cmpeqp %6, %5141 %11:intregs = C2_muxii %10, 0, -1142 %12:doubleregs = A2_addsp %11, %6143 %13:doubleregs = S2_asl_i_p %8, 2144 %14:intregs = S2_setbit_i %13.isub_lo, 1145 %15:intregs = C2_mux %10, %13.isub_lo, %14146 %16:predregs = C2_cmpeqp %12, %5147 %17:intregs = C2_muxii %16, 0, -1148 %18:doubleregs = A2_addsp %17, %12149 %19:intregs = S2_setbit_i %15, 0150 %20:intregs = C2_mux %16, %15, %19151 %21:predregs = C2_cmpeqp %18, %5152 %22:intregs = C2_muxii %21, 0, -1153 %23:doubleregs = A2_addsp %22, %18154 %24:intregs = S2_asl_i_r %20, 2155 %25:intregs = S2_extractu %8.isub_lo, 2, 28156 %26:intregs = S2_asl_i_r_or %25, %13.isub_hi, 2157 %27:intregs = S2_setbit_i %24, 1158 %28:intregs = C2_mux %21, %24, %27159 %29:predregs = C2_cmpeqp %23, %5160 %30:intregs = C2_muxii %29, 0, -1161 %7:doubleregs = A2_addsp %30, %23162 %31:intregs = S2_setbit_i %28, 0163 %32:intregs = C2_mux %29, %28, %31164 %9:doubleregs = REG_SEQUENCE %26, %subreg.isub_hi, %32, %subreg.isub_lo165 ENDLOOP0 %bb.1, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0166 J2_jump %bb.2, implicit-def dead $pc167 168 bb.2:169 successors: %bb.3(0x80000000)170 171 S2_storerdgp @_dp_ctrl_calc_tu_temp2_fp, %9, implicit $gp172 %33:intregs = A2_tfrsi 0173 %34:intregs = PS_fi %stack.0.rem.i11.i, 0174 %35:intregs = A2_tfrsi 0175 %36:doubleregs = L2_loadrd_io %stack.0.rem.i11.i, 0176 %37:doubleregs = A2_tfrpi 124177 %38:intregs = A2_tfrsi -1000178 %39:intregs = A2_tfrsi -1179 J2_loop0i %bb.3, 4, implicit-def $lc0, implicit-def $sa0, implicit-def $usr180 181 bb.3 (machine-block-address-taken):182 successors: %bb.4(0x04000000), %bb.3(0x7c000000)183 184 %40:doubleregs = PHI %36, %bb.2, %41, %bb.3185 %42:intregs = PHI %35, %bb.2, %43, %bb.3186 %44:intregs = PHI %33, %bb.2, %45, %bb.3187 %46:doubleregs = S2_lsr_i_p %40, 3188 %47:predregs = C2_cmpgtup %46, %37189 %48:intregs = C2_mux %47, %38, %33190 %49:intregs = C2_mux %47, %39, %33191 %50:doubleregs = REG_SEQUENCE %49, %subreg.isub_hi, %48, %subreg.isub_lo192 %51:doubleregs = A2_addp %50, %40193 %52:intregs = S2_asl_i_r %42, 2194 %53:intregs = S2_extractu %42, 2, 30195 %45:intregs = S2_asl_i_r_or %53, %44, 2196 %54:intregs = S2_setbit_i %52, 1197 %55:intregs = C2_mux %47, %54, %52198 %56:doubleregs = S2_lsr_i_p %51, 3199 %57:predregs = C2_cmpgtup %56, %37200 %58:intregs = C2_mux %57, %38, %33201 %59:intregs = C2_mux %57, %39, %33202 %60:doubleregs = REG_SEQUENCE %59, %subreg.isub_hi, %58, %subreg.isub_lo203 %41:doubleregs = A2_addp %60, %51204 %61:intregs = S2_setbit_i %55, 0205 %43:intregs = C2_mux %57, %61, %55206 ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0207 J2_jump %bb.4, implicit-def dead $pc208 209 bb.4:210 S2_storerigp @_dp_ctrl_calc_tu_temp1_fp, %43, implicit $gp211 %62:intregs = A2_tfrsi 0212 %63:doubleregs = REG_SEQUENCE %43, %subreg.isub_lo, %62, %subreg.isub_hi213 S2_storerdgp @dp_panel_update_tu_timings___trans_tmp_5, %63, implicit $gp214 S2_storerdgp @_dp_ctrl_calc_tu___trans_tmp_8, %9, implicit $gp215 PS_jmpret $r31, implicit-def dead $pc216 217...218