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1; RUN: llc -mtriple=hexagon -mcpu=hexagonv67t < %s | FileCheck %s2; RUN: llc -mtriple=hexagon -mcpu=hexagonv65 < %s | FileCheck --check-prefix=CHECK-BIG %s3 4; Test that the tiny core architecture generates 3 slot packets at most and5; a single load/store per packet at most.6 7; CHECK: loop0(.LBB0_[[LOOP:.]],8; CHECK: .LBB0_[[LOOP]]:9; CHECK: {10; CHECK-NEXT: mpy11; CHECK-NEXT: combine12; CHECK-NEXT: memw13; CHECK-NEXT: }14; CHECK: memw15; CHECK: } :endloop016 17; Test the loop contains a single packet with 4 instructions.18; CHECK-BIG: loop0(.LBB0_[[LOOP:.]],19; CHECK-BIG: .LBB0_[[LOOP]]:20; CHECK-BIG: {21; CHECK-BIG: += mpyi22; CHECK-BIG-NEXT: = combine23; CHECK-BIG-NEXT: = memw24; CHECK-BIG-NEXT: = memw25; CHECK-BIG-NEXT: } :endloop026 27define i32 @test(ptr noalias nocapture readonly %a, ptr noalias nocapture readonly %b, i32 %n) local_unnamed_addr #0 {28entry:29 %cmp8 = icmp sgt i32 %n, 030 br i1 %cmp8, label %for.body, label %for.end31 32for.body:33 %sum.010 = phi i32 [ %add, %for.body ], [ 0, %entry ]34 %arrayidx.phi = phi ptr [ %arrayidx.inc, %for.body ], [ %a, %entry ]35 %arrayidx1.phi = phi ptr [ %arrayidx1.inc, %for.body ], [ %b, %entry ]36 %i.09 = phi i32 [ %inc, %for.body ], [ 0, %entry ]37 %0 = load i32, ptr %arrayidx.phi, align 438 %1 = load i32, ptr %arrayidx1.phi, align 439 %mul = mul nsw i32 %1, %040 %add = add nsw i32 %mul, %sum.01041 %inc = add nuw nsw i32 %i.09, 142 %exitcond = icmp eq i32 %inc, %n43 %arrayidx.inc = getelementptr i32, ptr %arrayidx.phi, i32 144 %arrayidx1.inc = getelementptr i32, ptr %arrayidx1.phi, i32 145 br i1 %exitcond, label %for.end, label %for.body46 47for.end:48 %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ]49 ret i32 %sum.0.lcssa50}51 52