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1; RUN: llc -mtriple=hexagon -enable-aa-sched-mi < %s | FileCheck %s2 3; The two memory addresses in the load and the memop below are trivially4; non-aliasing. However, there are some cases where the scheduler cannot5; determine this - in this case, it is because of the use of memops, that on the6; surface. do not have only one mem operand. However, the backend knows MIs and7; can step in and help some cases. In our case, if the base registers are the8; same and the offsets different and the memory access size is such that9; the two accesses won't overlap, we can tell the scheduler that there is no10; dependence due to aliasing between the two instructions.11; In the example below, this allows the load to be packetized with the memop.12; CHECK: {13; CHECK: r{{[0-9]*}} = memw(r{{[0-9]*}}+#4)14; CHECK-NEXT: memw(r{{[0-9]*}}+#0) += #315; CHECK: }16 17@g0 = common global [10 x i32] zeroinitializer, align 818 19; Function Attrs: nounwind20define void @f0(ptr nocapture %a0) #0 {21b0:22 %v0 = load i32, ptr %a0, align 4, !tbaa !023 %v1 = add nsw i32 %v0, 324 store i32 %v1, ptr %a0, align 4, !tbaa !025 %v2 = getelementptr inbounds i32, ptr %a0, i32 126 %v3 = load i32, ptr %v2, align 4, !tbaa !027 store i32 %v3, ptr @g0, align 8, !tbaa !028 ret void29}30 31attributes #0 = { nounwind "target-cpu"="hexagonv60" }32 33!0 = !{!1, !1, i64 0}34!1 = !{!"int", !2}35!2 = !{!"omnipotent char", !3}36!3 = !{!"Simple C/C++ TBAA"}37