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1; RUN: llc -mtriple=hexagon -O2 < %s2; REQUIRES: asserts3 4; This file used to fail with an "UNREACHABLE executed!" in Post-RA pseudo5; instruction expansion pass due to a bug in the TwoAddressInstructionPass we6; were not handling sub register indexes when rewriting tied operands.7 8target triple = "hexagon"9 10%0 = type { i8, i8, %1, i32, i32, %7, i8, i8, %8, i8, i32, i16, i16, [2500 x i8], i16, i16, i16, ptr, [1024 x i8], i32, i32, i32, i32, i32, i8 }11%1 = type { i8, %2, i8, i8, i32 }12%2 = type { %3 }13%3 = type { i8, [256 x i8], %4, i8, i16, i32 }14%4 = type { %5 }15%5 = type { %6 }16%6 = type { [2 x i64] }17%7 = type { i32, i8 }18%8 = type { %7, i32, i32, %1 }19%9 = type { %10, ptr }20%10 = type { i16, i16, i32 }21%11 = type { i8, i32 }22 23@g0 = external hidden global [2 x %0], align 824@g1 = external hidden constant %9, align 425@g2 = external hidden constant %9, align 426@g3 = external hidden constant %9, align 427@g4 = external hidden constant %9, align 428 29; Function Attrs: optsize30declare void @f0(ptr, i32, i32, i32) #031 32; Function Attrs: nounwind optsize ssp33define hidden fastcc void @f1(i64 %a0, i8 zeroext %a1, i8 zeroext %a2) #1 {34b0:35 %v0 = alloca %11, align 436 %v1 = icmp ne i8 %a1, 037 %v2 = trunc i64 %a0 to i3238 br i1 %v1, label %b1, label %b439 40b1: ; preds = %b041 call void @f0(ptr @g1, i32 %v2, i32 0, i32 0) #242 %v3 = getelementptr inbounds [2 x %0], ptr @g0, i32 0, i32 %v2, i32 743 store i8 1, ptr %v3, align 144 %v4 = icmp eq i8 %a2, 045 br i1 %v4, label %b4, label %b246 47b2: ; preds = %b148 store i8 0, ptr %v0, align 449 %v6 = getelementptr inbounds %11, ptr %v0, i32 0, i32 150 store i32 0, ptr %v6, align 451 %v7 = getelementptr inbounds [2 x %0], ptr @g0, i32 0, i32 %v2, i32 352 %v8 = load i32, ptr %v7, align 853 %v9 = getelementptr inbounds [2 x %0], ptr @g0, i32 0, i32 %v2, i32 454 %v10 = load i32, ptr %v9, align 455 %v11 = getelementptr inbounds [2 x %0], ptr @g0, i32 0, i32 %v2, i32 1956 %v12 = load i32, ptr %v11, align 457 %v13 = call zeroext i8 @f2(i64 %a0, i32 %v8, i32 %v10, i32 %v12, i8 zeroext 0, ptr %v0) #258 %v14 = icmp eq i8 %v13, 059 br i1 %v14, label %b4, label %b360 61b3: ; preds = %b262 %v15 = zext i8 %v13 to i3263 call void @f0(ptr @g2, i32 %v15, i32 %v2, i32 0) #264 br label %b465 66b4: ; preds = %b3, %b2, %b1, %b067 %v16 = getelementptr inbounds [2 x %0], ptr @g0, i32 0, i32 %v2, i32 168 %v17 = load i8, ptr %v16, align 169 %v18 = zext i8 %v17 to i3270 switch i32 %v18, label %b14 [71 i32 2, label %b1172 i32 1, label %b573 i32 4, label %b874 i32 3, label %b1175 ]76 77b5: ; preds = %b478 call void @f0(ptr @g3, i32 %v2, i32 0, i32 0) #279 br i1 %v1, label %b7, label %b680 81b6: ; preds = %b582 call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 1, i32 1) #083 br label %b1484 85b7: ; preds = %b586 call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 0, i32 1) #087 br label %b1488 89b8: ; preds = %b490 call void @f0(ptr @g4, i32 %v2, i32 0, i32 0) #291 %v19 = getelementptr inbounds [2 x %0], ptr @g0, i32 0, i32 %v2, i32 692 store i8 1, ptr %v19, align 893 br i1 %v1, label %b10, label %b994 95b9: ; preds = %b896 call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 1, i32 1) #097 br label %b1498 99b10: ; preds = %b8100 call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 0, i32 1) #0101 br label %b14102 103b11: ; preds = %b4, %b4104 br i1 %v1, label %b13, label %b12105 106b12: ; preds = %b11107 call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 1, i32 1) #0108 br label %b14109 110b13: ; preds = %b11111 call fastcc void @f3(i64 %a0, i8 zeroext 0, i8 zeroext 0, i32 1) #0112 br label %b14113 114b14: ; preds = %b13, %b12, %b10, %b9, %b7, %b6, %b4115 ret void116}117 118; Function Attrs: optsize119declare zeroext i8 @f2(i64, i32, i32, i32, i8 zeroext, ptr) #0120 121; Function Attrs: nounwind optsize ssp122declare hidden fastcc void @f3(i64, i8 zeroext, i8 zeroext, i32) #1123 124attributes #0 = { optsize }125attributes #1 = { nounwind optsize ssp }126attributes #2 = { nounwind optsize }127