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1; RUN: llc -mtriple=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s2; CHECK: vmemu(r{{[0-9]+}}+#0) = v{{[0-9]*}}3 4target triple = "hexagon"5 6; Function Attrs: nounwind7define void @f0(ptr %a0, i32 %a1, ptr %a2, i32 %a3, ptr %a4) #0 {8b0:9 %v0 = alloca ptr, align 410 %v1 = alloca i32, align 411 %v2 = alloca ptr, align 412 %v3 = alloca i32, align 413 %v4 = alloca ptr, align 414 %v5 = alloca i32, align 415 %v6 = alloca i32, align 416 %v7 = alloca i32, align 417 %v8 = alloca i32, align 418 %v9 = alloca i32, align 419 %v10 = alloca <16 x i32>, align 6420 %v11 = alloca <16 x i32>, align 6421 %v12 = alloca <16 x i32>, align 6422 %v13 = alloca <16 x i32>, align 6423 %v14 = alloca <16 x i32>, align 6424 %v15 = alloca <16 x i32>, align 6425 %v16 = alloca <16 x i32>, align 6426 %v17 = alloca <16 x i32>, align 6427 %v18 = alloca <16 x i32>, align 6428 %v19 = alloca <16 x i32>, align 6429 %v20 = alloca <16 x i32>, align 6430 store ptr %a0, ptr %v0, align 431 store i32 %a1, ptr %v1, align 432 store ptr %a2, ptr %v2, align 433 store i32 %a3, ptr %v3, align 434 store ptr %a4, ptr %v4, align 435 %v21 = load i32, ptr %v1, align 436 %v22 = ashr i32 %v21, 1637 %v23 = and i32 65535, %v2238 store i32 %v23, ptr %v8, align 439 %v24 = load i32, ptr %v1, align 440 %v25 = and i32 65535, %v2441 store i32 %v25, ptr %v5, align 442 %v26 = load i32, ptr %v3, align 443 %v27 = and i32 65535, %v2644 store i32 %v27, ptr %v6, align 445 %v28 = load i32, ptr %v3, align 446 %v29 = ashr i32 %v28, 1647 %v30 = and i32 65535, %v2948 store i32 %v30, ptr %v9, align 449 %v31 = load ptr, ptr %v4, align 450 %v33 = load <16 x i32>, ptr %v31, align 6451 store <16 x i32> %v33, ptr %v10, align 6452 %v34 = load ptr, ptr %v4, align 453 %v35 = getelementptr inbounds i8, ptr %v34, i32 6454 %v37 = load <16 x i32>, ptr %v35, align 6455 store <16 x i32> %v37, ptr %v12, align 6456 %v38 = load i32, ptr %v9, align 457 store i32 %v38, ptr %v7, align 458 br label %b159 60b1: ; preds = %b3, %b061 %v39 = load i32, ptr %v7, align 462 %v40 = icmp sge i32 %v39, 063 br i1 %v40, label %b2, label %b464 65b2: ; preds = %b166 %v41 = load ptr, ptr %v0, align 467 %v43 = load <16 x i32>, ptr %v41, align 468 store <16 x i32> %v43, ptr %v14, align 6469 %v44 = load i32, ptr %v5, align 470 %v45 = load ptr, ptr %v0, align 471 %v46 = getelementptr inbounds i8, ptr %v45, i32 %v4472 store ptr %v46, ptr %v0, align 473 %v47 = load <16 x i32>, ptr %v14, align 6474 %v48 = load <16 x i32>, ptr %v10, align 6475 %v49 = call <16 x i32> @llvm.hexagon.V6.vrdelta(<16 x i32> %v47, <16 x i32> %v48)76 store <16 x i32> %v49, ptr %v15, align 6477 %v50 = load <16 x i32>, ptr %v14, align 6478 %v51 = load <16 x i32>, ptr %v12, align 6479 %v52 = call <16 x i32> @llvm.hexagon.V6.vrdelta(<16 x i32> %v50, <16 x i32> %v51)80 store <16 x i32> %v52, ptr %v17, align 6481 %v53 = load <16 x i32>, ptr %v15, align 6482 %v54 = load <16 x i32>, ptr %v17, align 6483 %v55 = call <16 x i32> @llvm.hexagon.V6.vavgub(<16 x i32> %v53, <16 x i32> %v54)84 store <16 x i32> %v55, ptr %v19, align 6485 %v56 = load ptr, ptr %v2, align 486 %v57 = load <16 x i32>, ptr %v19, align 6487 call void asm sideeffect " vmemu($0) = $1;\0A", "r,v,~{memory}"(ptr %v56, <16 x i32> %v57) #2, !srcloc !088 br label %b389 90b3: ; preds = %b291 %v58 = load i32, ptr %v6, align 492 %v59 = load i32, ptr %v7, align 493 %v60 = sub nsw i32 %v59, %v5894 store i32 %v60, ptr %v7, align 495 br label %b196 97b4: ; preds = %b198 ret void99}100 101; Function Attrs: nounwind readnone102declare <16 x i32> @llvm.hexagon.V6.vrdelta(<16 x i32>, <16 x i32>) #1103 104; Function Attrs: nounwind readnone105declare <16 x i32> @llvm.hexagon.V6.vavgub(<16 x i32>, <16 x i32>) #1106 107attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }108attributes #1 = { nounwind readnone }109attributes #2 = { nounwind }110 111!0 = !{i32 1708}112