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1; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s2; CHECK: vsplat3 4target triple = "hexagon"5 6@g0 = common global [15 x <16 x i32>] zeroinitializer, align 647@g1 = common global [15 x <32 x i32>] zeroinitializer, align 1288 9; Function Attrs: nounwind10define void @f0() #0 {11b0:12 %v0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)13 store <16 x i32> %v0, ptr @g0, align 64, !tbaa !014 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2)15 store <16 x i32> %v1, ptr getelementptr inbounds ([15 x <16 x i32>], ptr @g0, i32 0, i32 1), align 64, !tbaa !016 %v2 = tail call <32 x i32> @llvm.hexagon.V6.vaddubh(<16 x i32> %v0, <16 x i32> %v1)17 store <32 x i32> %v2, ptr @g1, align 128, !tbaa !018 store <32 x i32> %v2, ptr getelementptr inbounds ([15 x <32 x i32>], ptr @g1, i32 0, i32 1), align 128, !tbaa !019 %v3 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 3)20 store <16 x i32> %v3, ptr getelementptr inbounds ([15 x <16 x i32>], ptr @g0, i32 0, i32 2), align 64, !tbaa !021 %v4 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 4)22 store <16 x i32> %v4, ptr getelementptr inbounds ([15 x <16 x i32>], ptr @g0, i32 0, i32 3), align 64, !tbaa !023 %v5 = tail call <32 x i32> @llvm.hexagon.V6.vaddubh(<16 x i32> %v3, <16 x i32> %v4)24 store <32 x i32> %v5, ptr getelementptr inbounds ([15 x <32 x i32>], ptr @g1, i32 0, i32 2), align 128, !tbaa !025 store <32 x i32> %v5, ptr getelementptr inbounds ([15 x <32 x i32>], ptr @g1, i32 0, i32 3), align 128, !tbaa !026 %v6 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 5)27 store <16 x i32> %v6, ptr getelementptr inbounds ([15 x <16 x i32>], ptr @g0, i32 0, i32 4), align 64, !tbaa !028 %v7 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 6)29 store <16 x i32> %v7, ptr getelementptr inbounds ([15 x <16 x i32>], ptr @g0, i32 0, i32 5), align 64, !tbaa !030 %v8 = tail call <32 x i32> @llvm.hexagon.V6.vaddubh(<16 x i32> %v6, <16 x i32> %v7)31 store <32 x i32> %v8, ptr getelementptr inbounds ([15 x <32 x i32>], ptr @g1, i32 0, i32 4), align 128, !tbaa !032 store <32 x i32> %v8, ptr getelementptr inbounds ([15 x <32 x i32>], ptr @g1, i32 0, i32 5), align 128, !tbaa !033 %v9 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 7)34 store <16 x i32> %v9, ptr getelementptr inbounds ([15 x <16 x i32>], ptr @g0, i32 0, i32 6), align 64, !tbaa !035 %v10 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 8)36 store <16 x i32> %v10, ptr getelementptr inbounds ([15 x <16 x i32>], ptr @g0, i32 0, i32 7), align 64, !tbaa !037 %v11 = tail call <32 x i32> @llvm.hexagon.V6.vaddubh(<16 x i32> %v9, <16 x i32> %v10)38 store <32 x i32> %v11, ptr getelementptr inbounds ([15 x <32 x i32>], ptr @g1, i32 0, i32 6), align 128, !tbaa !039 store <32 x i32> %v11, ptr getelementptr inbounds ([15 x <32 x i32>], ptr @g1, i32 0, i32 7), align 128, !tbaa !040 ret void41}42 43; Function Attrs: nounwind readnone44declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #145 46; Function Attrs: nounwind readnone47declare <32 x i32> @llvm.hexagon.V6.vaddubh(<16 x i32>, <16 x i32>) #148 49attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }50attributes #1 = { nounwind readnone }51 52!0 = !{!1, !1, i64 0}53!1 = !{!"omnipotent char", !2, i64 0}54!2 = !{!"Simple C/C++ TBAA"}55