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1; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s2; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s3 4; CHECK: v{{[0-9]*}} = vxor(v{{[0-9]*}},v{{[0-9]*}})5; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.b += v{{[0-9]*}}.b6; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.b -= v{{[0-9]*}}.b7; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.h += v{{[0-9]*}}.h8; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.h -= v{{[0-9]*}}.h9; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.w += v{{[0-9]*}}.w10; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.w -= v{{[0-9]*}}.w11; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.b += v{{[0-9]*}}.b12; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.b -= v{{[0-9]*}}.b13; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.h += v{{[0-9]*}}.h14; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.h -= v{{[0-9]*}}.h15; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.w += v{{[0-9]*}}.w16; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.w -= v{{[0-9]*}}.w17 18target triple = "hexagon"19 20@g0 = common global <16 x i32> zeroinitializer, align 6421@g1 = common global <16 x i32> zeroinitializer, align 6422@g2 = common global <16 x i32> zeroinitializer, align 6423@g3 = common global <16 x i32> zeroinitializer, align 6424 25; Function Attrs: nounwind26define i32 @f0() #0 {27b0:28 %v0 = call <16 x i32> @llvm.hexagon.V6.vd0()29 store <16 x i32> %v0, ptr @g0, align 6430 %v1 = call <16 x i32> @llvm.hexagon.V6.vd0()31 store <16 x i32> %v1, ptr @g1, align 6432 %v2 = call <16 x i32> @llvm.hexagon.V6.vd0()33 store <16 x i32> %v2, ptr @g2, align 6434 %v3 = load <16 x i32>, ptr @g3, align 6435 %v4 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v3, i32 -1)36 %v5 = load <16 x i32>, ptr @g2, align 6437 %v6 = load <16 x i32>, ptr @g1, align 6438 %v7 = call <16 x i32> @llvm.hexagon.V6.vaddbq(<64 x i1> %v4, <16 x i32> %v5, <16 x i32> %v6)39 store <16 x i32> %v7, ptr @g2, align 6440 %v8 = load <16 x i32>, ptr @g3, align 6441 %v9 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v8, i32 -1)42 %v10 = load <16 x i32>, ptr @g2, align 6443 %v11 = load <16 x i32>, ptr @g1, align 6444 %v12 = call <16 x i32> @llvm.hexagon.V6.vsubbq(<64 x i1> %v9, <16 x i32> %v10, <16 x i32> %v11)45 store <16 x i32> %v12, ptr @g2, align 6446 %v13 = load <16 x i32>, ptr @g3, align 6447 %v14 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v13, i32 -1)48 %v15 = load <16 x i32>, ptr @g2, align 6449 %v16 = load <16 x i32>, ptr @g1, align 6450 %v17 = call <16 x i32> @llvm.hexagon.V6.vaddhq(<64 x i1> %v14, <16 x i32> %v15, <16 x i32> %v16)51 store <16 x i32> %v17, ptr @g2, align 6452 %v18 = load <16 x i32>, ptr @g3, align 6453 %v19 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v18, i32 -1)54 %v20 = load <16 x i32>, ptr @g2, align 6455 %v21 = load <16 x i32>, ptr @g1, align 6456 %v22 = call <16 x i32> @llvm.hexagon.V6.vsubhq(<64 x i1> %v19, <16 x i32> %v20, <16 x i32> %v21)57 store <16 x i32> %v22, ptr @g2, align 6458 %v23 = load <16 x i32>, ptr @g3, align 6459 %v24 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v23, i32 -1)60 %v25 = load <16 x i32>, ptr @g2, align 6461 %v26 = load <16 x i32>, ptr @g1, align 6462 %v27 = call <16 x i32> @llvm.hexagon.V6.vaddwq(<64 x i1> %v24, <16 x i32> %v25, <16 x i32> %v26)63 store <16 x i32> %v27, ptr @g2, align 6464 %v28 = load <16 x i32>, ptr @g3, align 6465 %v29 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v28, i32 -1)66 %v30 = load <16 x i32>, ptr @g2, align 6467 %v31 = load <16 x i32>, ptr @g1, align 6468 %v32 = call <16 x i32> @llvm.hexagon.V6.vsubwq(<64 x i1> %v29, <16 x i32> %v30, <16 x i32> %v31)69 store <16 x i32> %v32, ptr @g2, align 6470 %v33 = load <16 x i32>, ptr @g3, align 6471 %v34 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v33, i32 -1)72 %v35 = load <16 x i32>, ptr @g2, align 6473 %v36 = load <16 x i32>, ptr @g1, align 6474 %v37 = call <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1> %v34, <16 x i32> %v35, <16 x i32> %v36)75 store <16 x i32> %v37, ptr @g2, align 6476 %v38 = load <16 x i32>, ptr @g3, align 6477 %v39 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v38, i32 -1)78 %v40 = load <16 x i32>, ptr @g2, align 6479 %v41 = load <16 x i32>, ptr @g1, align 6480 %v42 = call <16 x i32> @llvm.hexagon.V6.vsubbnq(<64 x i1> %v39, <16 x i32> %v40, <16 x i32> %v41)81 store <16 x i32> %v42, ptr @g2, align 6482 %v43 = load <16 x i32>, ptr @g3, align 6483 %v44 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v43, i32 -1)84 %v45 = load <16 x i32>, ptr @g2, align 6485 %v46 = load <16 x i32>, ptr @g1, align 6486 %v47 = call <16 x i32> @llvm.hexagon.V6.vaddhnq(<64 x i1> %v44, <16 x i32> %v45, <16 x i32> %v46)87 store <16 x i32> %v47, ptr @g2, align 6488 %v48 = load <16 x i32>, ptr @g3, align 6489 %v49 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v48, i32 -1)90 %v50 = load <16 x i32>, ptr @g2, align 6491 %v51 = load <16 x i32>, ptr @g1, align 6492 %v52 = call <16 x i32> @llvm.hexagon.V6.vsubhnq(<64 x i1> %v49, <16 x i32> %v50, <16 x i32> %v51)93 store <16 x i32> %v52, ptr @g2, align 6494 %v53 = load <16 x i32>, ptr @g3, align 6495 %v54 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v53, i32 -1)96 %v55 = load <16 x i32>, ptr @g2, align 6497 %v56 = load <16 x i32>, ptr @g1, align 6498 %v57 = call <16 x i32> @llvm.hexagon.V6.vaddwnq(<64 x i1> %v54, <16 x i32> %v55, <16 x i32> %v56)99 store <16 x i32> %v57, ptr @g2, align 64100 %v58 = load <16 x i32>, ptr @g3, align 64101 %v59 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v58, i32 -1)102 %v60 = load <16 x i32>, ptr @g2, align 64103 %v61 = load <16 x i32>, ptr @g1, align 64104 %v62 = call <16 x i32> @llvm.hexagon.V6.vsubwnq(<64 x i1> %v59, <16 x i32> %v60, <16 x i32> %v61)105 store <16 x i32> %v62, ptr @g2, align 64106 ret i32 0107}108 109; Function Attrs: nounwind readnone110declare <16 x i32> @llvm.hexagon.V6.vd0() #1111 112; Function Attrs: nounwind readnone113declare <16 x i32> @llvm.hexagon.V6.vaddbq(<64 x i1>, <16 x i32>, <16 x i32>) #1114 115; Function Attrs: nounwind readnone116declare <16 x i32> @llvm.hexagon.V6.vsubbq(<64 x i1>, <16 x i32>, <16 x i32>) #1117 118; Function Attrs: nounwind readnone119declare <16 x i32> @llvm.hexagon.V6.vaddhq(<64 x i1>, <16 x i32>, <16 x i32>) #1120 121; Function Attrs: nounwind readnone122declare <16 x i32> @llvm.hexagon.V6.vsubhq(<64 x i1>, <16 x i32>, <16 x i32>) #1123 124; Function Attrs: nounwind readnone125declare <16 x i32> @llvm.hexagon.V6.vaddwq(<64 x i1>, <16 x i32>, <16 x i32>) #1126 127; Function Attrs: nounwind readnone128declare <16 x i32> @llvm.hexagon.V6.vsubwq(<64 x i1>, <16 x i32>, <16 x i32>) #1129 130; Function Attrs: nounwind readnone131declare <16 x i32> @llvm.hexagon.V6.vaddbnq(<64 x i1>, <16 x i32>, <16 x i32>) #1132 133; Function Attrs: nounwind readnone134declare <16 x i32> @llvm.hexagon.V6.vsubbnq(<64 x i1>, <16 x i32>, <16 x i32>) #1135 136; Function Attrs: nounwind readnone137declare <16 x i32> @llvm.hexagon.V6.vaddhnq(<64 x i1>, <16 x i32>, <16 x i32>) #1138 139; Function Attrs: nounwind readnone140declare <16 x i32> @llvm.hexagon.V6.vsubhnq(<64 x i1>, <16 x i32>, <16 x i32>) #1141 142; Function Attrs: nounwind readnone143declare <16 x i32> @llvm.hexagon.V6.vaddwnq(<64 x i1>, <16 x i32>, <16 x i32>) #1144 145; Function Attrs: nounwind readnone146declare <16 x i32> @llvm.hexagon.V6.vsubwnq(<64 x i1>, <16 x i32>, <16 x i32>) #1147 148; Function Attrs: nounwind readnone149declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1150 151attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }152attributes #1 = { nounwind readnone }153