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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; Test that we generate a .cur4 5; CHECK: v{{[0-9]*}}.cur6 7; Function Attrs: nounwind8define void @f0(ptr noalias nocapture readonly %a0, i32 %a1, i32 %a2, ptr %a3, ptr %a4) #0 {9b0:10 br i1 undef, label %b1, label %b311 12b1: ; preds = %b013 br label %b214 15b2: ; preds = %b2, %b116 %v0 = phi ptr [ %a0, %b1 ], [ %v4, %b2 ]17 %v1 = phi i32 [ 0, %b1 ], [ %v23, %b2 ]18 %v2 = phi <16 x i32> [ zeroinitializer, %b1 ], [ %v6, %b2 ]19 %v3 = phi <16 x i32> [ zeroinitializer, %b1 ], [ zeroinitializer, %b2 ]20 %v4 = getelementptr inbounds i8, ptr %v0, i32 6421 %v6 = load <16 x i32>, ptr %v4, align 64, !tbaa !022 %v7 = load <16 x i32>, ptr %a3, align 64, !tbaa !023 %v8 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v6, <16 x i32> %v2, i32 4)24 %v9 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> zeroinitializer, <16 x i32> %v3, i32 4)25 %v10 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v7, <16 x i32> zeroinitializer, i32 4)26 %v11 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v8, <16 x i32> %v2)27 %v12 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v10, <16 x i32> zeroinitializer)28 %v13 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v11, i32 0, i32 0)29 %v14 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v13, <32 x i32> zeroinitializer, i32 undef, i32 0)30 %v15 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v14, <32 x i32> undef, i32 undef, i32 0)31 %v16 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v15)32 %v17 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %v16, <16 x i32> undef, i32 %a1)33 %v18 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> undef, <16 x i32> %v17)34 store <16 x i32> %v18, ptr %a3, align 64, !tbaa !035 %v19 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> zeroinitializer, <32 x i32> %v12, i32 undef, i32 1)36 %v20 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v19)37 %v21 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %v20, <16 x i32> undef, i32 %a1)38 %v22 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v21, <16 x i32> undef)39 store <16 x i32> %v22, ptr %a4, align 64, !tbaa !040 %v23 = add nsw i32 %v1, 6441 %v24 = icmp slt i32 %v23, %a242 br i1 %v24, label %b2, label %b343 44b3: ; preds = %b2, %b045 ret void46}47 48declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #149declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #150declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #151declare <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32>, <32 x i32>, i32, i32) #152declare <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32>, <16 x i32>, i32) #153declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #154declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #155 56attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }57attributes #1 = { nounwind readnone }58 59!0 = !{!1, !1, i64 0}60!1 = !{!"omnipotent char", !2, i64 0}61!2 = !{!"Simple C/C++ TBAA"}62