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1; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s2 3; CHECK: vmem(r{{[0-9]+}}++#1)4; CHECK: vmem(r{{[0-9]+}}++#1)5; CHECK: vmem(r{{[0-9]+}}++#1)6; CHECK: vmem(r{{[0-9]+}}++#1)7 8target triple = "hexagon"9 10; Function Attrs: nounwind11define void @f0(ptr nocapture readonly %a0, i32 %a1, i32 %a2, i32 %a3, ptr nocapture %a4, i32 %a5) #0 {12b0:13 %v0 = ashr i32 %a3, 214 %v1 = ashr i32 %a3, 115 %v2 = add i32 %v1, %v016 %v3 = icmp sgt i32 %a2, 017 br i1 %v3, label %b1, label %b818 19b1: ; preds = %b020 %v4 = sdiv i32 %a1, 6421 %v5 = icmp sgt i32 %a1, 6322 br label %b223 24b2: ; preds = %b6, %b125 %v6 = phi i32 [ 0, %b1 ], [ %v56, %b6 ]26 %v7 = ashr exact i32 %v6, 127 %v8 = mul nsw i32 %v7, %a328 br i1 %v5, label %b3, label %b629 30b3: ; preds = %b231 %v9 = add nsw i32 %v6, 132 %v10 = mul nsw i32 %v9, %a533 %v11 = mul nsw i32 %v6, %a534 %v12 = add i32 %v2, %v835 %v13 = add i32 %v8, %v036 %v14 = add i32 %v8, %v137 %v15 = getelementptr inbounds i8, ptr %a4, i32 %v1038 %v16 = getelementptr inbounds i8, ptr %a4, i32 %v1139 %v17 = getelementptr inbounds i16, ptr %a0, i32 %v1240 %v18 = getelementptr inbounds i16, ptr %a0, i32 %v1341 %v19 = getelementptr inbounds i16, ptr %a0, i32 %v1442 %v20 = getelementptr inbounds i16, ptr %a0, i32 %v843 br label %b444 45b4: ; preds = %b4, %b346 %v27 = phi i32 [ 0, %b3 ], [ %v54, %b4 ]47 %v28 = phi ptr [ %v20, %b3 ], [ %v34, %b4 ]48 %v29 = phi ptr [ %v19, %b3 ], [ %v36, %b4 ]49 %v30 = phi ptr [ %v18, %b3 ], [ %v38, %b4 ]50 %v31 = phi ptr [ %v17, %b3 ], [ %v40, %b4 ]51 %v32 = phi ptr [ %v15, %b3 ], [ %v53, %b4 ]52 %v33 = phi ptr [ %v16, %b3 ], [ %v52, %b4 ]53 %v34 = getelementptr inbounds <16 x i32>, ptr %v28, i32 154 %v35 = load <16 x i32>, ptr %v28, align 64, !tbaa !055 %v36 = getelementptr inbounds <16 x i32>, ptr %v29, i32 156 %v37 = load <16 x i32>, ptr %v29, align 64, !tbaa !057 %v38 = getelementptr inbounds <16 x i32>, ptr %v30, i32 158 %v39 = load <16 x i32>, ptr %v30, align 64, !tbaa !059 %v40 = getelementptr inbounds <16 x i32>, ptr %v31, i32 160 %v41 = load <16 x i32>, ptr %v31, align 64, !tbaa !061 %v42 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v35, <16 x i32> %v37)62 %v43 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v35, <16 x i32> %v37)63 %v44 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v39, <16 x i32> %v41)64 %v45 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v39, <16 x i32> %v41)65 %v46 = tail call <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32> %v42, <16 x i32> %v44)66 %v47 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %v42, <16 x i32> %v44)67 %v48 = tail call <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32> %v43, <16 x i32> %v45)68 %v49 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %v43, <16 x i32> %v45)69 %v50 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v47, <16 x i32> %v46)70 %v51 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v49, <16 x i32> %v48)71 %v52 = getelementptr inbounds <16 x i32>, ptr %v33, i32 172 store <16 x i32> %v50, ptr %v33, align 64, !tbaa !073 %v53 = getelementptr inbounds <16 x i32>, ptr %v32, i32 174 store <16 x i32> %v51, ptr %v32, align 64, !tbaa !075 %v54 = add nsw i32 %v27, 176 %v55 = icmp slt i32 %v54, %v477 br i1 %v55, label %b4, label %b578 79b5: ; preds = %b480 br label %b681 82b6: ; preds = %b5, %b283 %v56 = add nsw i32 %v6, 284 %v57 = icmp slt i32 %v56, %a285 br i1 %v57, label %b2, label %b786 87b7: ; preds = %b688 br label %b889 90b8: ; preds = %b7, %b091 ret void92}93 94; Function Attrs: nounwind readnone95declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #196 97; Function Attrs: nounwind readnone98declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #199 100; Function Attrs: nounwind readnone101declare <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32>, <16 x i32>) #1102 103; Function Attrs: nounwind readnone104declare <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32>, <16 x i32>) #1105 106; Function Attrs: nounwind readnone107declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1108 109attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }110attributes #1 = { nounwind readnone }111 112!0 = !{!1, !1, i64 0}113!1 = !{!"omnipotent char", !2, i64 0}114!2 = !{!"Simple C/C++ TBAA"}115