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1; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s2; CHECK: v{{[0-9]+}} = vsplat(r{{[0-9]+}})3; CHECK: .comm g0,256,2564; CHECK: .comm g1,128,1285 6target triple = "hexagon"7 8@g0 = common global <64 x i32> zeroinitializer, align 2569@g1 = common global <32 x i32> zeroinitializer, align 12810 11; Function Attrs: nounwind12define i32 @f0() #0 {13b0:14 %v0 = alloca i32, align 415 store i32 0, ptr %v016 %v1 = call i32 @f1(i8 zeroext 0)17 call void @f2()18 %v2 = call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 1)19 %v3 = call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 2)20 %v4 = call <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32> %v2, <32 x i32> %v3)21 %v5 = call <64 x i32> @llvm.hexagon.V6.vtmpyhb.128B(<64 x i32> %v4, i32 12)22 store <64 x i32> %v5, ptr @g0, align 25623 call void @f3(i32 2048, ptr @g0)24 ret i32 025}26 27declare i32 @f1(i8 zeroext) #028 29declare void @f2(...) #030 31; Function Attrs: nounwind readnone32declare <64 x i32> @llvm.hexagon.V6.vtmpyhb.128B(<64 x i32>, i32) #133 34; Function Attrs: nounwind readnone35declare <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32>, <32 x i32>) #136 37; Function Attrs: nounwind readnone38declare <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32) #139 40declare void @f3(i32, ptr) #041 42attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }43attributes #1 = { nounwind readnone }44