68 lines · plain
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; CHECK: if (p{{[0-3]}}) v{{[0-9]+}} = v{{[0-9]+}}4 5target triple = "hexagon"6 7; Function Attrs: nounwind8define void @fast9_detect_coarse(ptr nocapture readnone %img, i32 %xsize, i32 %stride, i32 %barrier, ptr nocapture %bitmask, i32 %boundary) #0 {9entry:10 %0 = mul i32 %boundary, -211 %sub = add i32 %0, %xsize12 %rem = and i32 %boundary, 6313 %add = add i32 %sub, %rem14 %1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 -1)15 %2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)16 %3 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %add)17 %4 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32> %2, <64 x i1> %3, i32 12)18 %and4 = and i32 %add, 51119 %cmp = icmp eq i32 %and4, 020 %sMaskR.0 = select i1 %cmp, <16 x i32> %1, <16 x i32> %421 %cmp547 = icmp sgt i32 %add, 022 br i1 %cmp547, label %for.body.lr.ph, label %for.end23 24for.body.lr.ph: ; preds = %entry25 %5 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %boundary)26 %6 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %5, i32 16843009)27 %7 = tail call <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32> %6)28 %8 = add i32 %rem, %xsize29 %9 = add i32 %8, -130 %10 = add i32 %9, %031 %11 = lshr i32 %10, 932 %12 = mul i32 %11, 1633 %13 = add nuw nsw i32 %12, 1634 %scevgep = getelementptr i32, ptr %bitmask, i32 %1335 br label %for.body36 37for.body: ; preds = %for.body.lr.ph, %for.body38 %i.050 = phi i32 [ %add, %for.body.lr.ph ], [ %sub6, %for.body ]39 %sMask.049 = phi <16 x i32> [ %7, %for.body.lr.ph ], [ %1, %for.body ]40 %optr.048 = phi ptr [ %bitmask, %for.body.lr.ph ], [ %incdec.ptr, %for.body ]41 %14 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> undef, <16 x i32> %sMask.049)42 %incdec.ptr = getelementptr inbounds <16 x i32>, ptr %optr.048, i32 143 store <16 x i32> %14, ptr %optr.048, align 6444 %sub6 = add nsw i32 %i.050, -51245 %cmp5 = icmp sgt i32 %sub6, 046 br i1 %cmp5, label %for.body, label %for.cond.for.end_crit_edge47 48for.cond.for.end_crit_edge: ; preds = %for.body49 br label %for.end50 51for.end: ; preds = %for.cond.for.end_crit_edge, %entry52 %optr.0.lcssa = phi ptr [ %scevgep, %for.cond.for.end_crit_edge ], [ %bitmask, %entry ]53 %15 = load <16 x i32>, ptr %optr.0.lcssa, align 6454 %16 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> %15, <16 x i32> %sMaskR.0)55 store <16 x i32> %16, ptr %optr.0.lcssa, align 6456 ret void57}58 59declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #160declare <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #161declare <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32>, <64 x i1>, i32) #162declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #163declare <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32>) #164declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #165 66attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }67attributes #1 = { nounwind readnone }68