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1; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s2 3; CHECK: v{{[0-9]+}}:{{[0-9]+}} = vcombine(v{{[0-9]+}},v{{[0-9]+}})4 5target triple = "hexagon"6 7; Function Attrs: nounwind8define void @f0(ptr nocapture readnone %a0, i32 %a1, i32 %a2, i32 %a3, ptr nocapture %a4, i32 %a5) #0 {9b0:10 %v1 = mul i32 %a5, -211 %v2 = add i32 %v1, %a112 %v3 = and i32 %a5, 6313 %v4 = add i32 %v2, %v314 %v5 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 -1)15 %v6 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)16 %v7 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %v4)17 %v8 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32> %v6, <64 x i1> %v7, i32 12)18 %v9 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v8, <16 x i32> %v8)19 %v10 = and i32 %v4, 51120 %v11 = icmp eq i32 %v10, 021 br i1 %v11, label %b1, label %b222 23b1: ; preds = %b024 %v12 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v5, <16 x i32> %v8)25 br label %b226 27b2: ; preds = %b1, %b028 %v13 = phi <32 x i32> [ %v12, %b1 ], [ %v9, %b0 ]29 %v14 = icmp sgt i32 %v4, 030 br i1 %v14, label %b3, label %b631 32b3: ; preds = %b233 %v15 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %a5)34 %v16 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v15, i32 16843009)35 %v17 = tail call <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32> %v16)36 %v18 = add i32 %v3, %a137 %v19 = add i32 %v18, -138 %v20 = add i32 %v19, %v139 %v21 = lshr i32 %v20, 940 %v22 = mul i32 %v21, 1641 %v23 = add nuw nsw i32 %v22, 1642 %v24 = getelementptr i32, ptr %a4, i32 %v2343 br label %b444 45b4: ; preds = %b4, %b346 %v25 = phi i32 [ %v4, %b3 ], [ %v30, %b4 ]47 %v26 = phi <16 x i32> [ %v17, %b3 ], [ %v5, %b4 ]48 %v27 = phi ptr [ %a4, %b3 ], [ %v29, %b4 ]49 %v28 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> undef, <16 x i32> %v26)50 %v29 = getelementptr inbounds <16 x i32>, ptr %v27, i32 151 store <16 x i32> %v28, ptr %v27, align 64, !tbaa !052 %v30 = add nsw i32 %v25, -51253 %v31 = icmp sgt i32 %v30, 054 br i1 %v31, label %b4, label %b555 56b5: ; preds = %b457 br label %b658 59b6: ; preds = %b5, %b260 %v33 = phi ptr [ %v24, %b5 ], [ %a4, %b2 ]61 %v34 = load <16 x i32>, ptr %v33, align 64, !tbaa !062 %v35 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v13)63 %v36 = tail call <16 x i32> @llvm.hexagon.V6.vand(<16 x i32> %v34, <16 x i32> %v35)64 store <16 x i32> %v36, ptr %v33, align 64, !tbaa !065 ret void66}67 68; Function Attrs: nounwind readnone69declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #170 71; Function Attrs: nounwind readnone72declare <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #173 74; Function Attrs: nounwind readnone75declare <16 x i32> @llvm.hexagon.V6.vandqrt.acc(<16 x i32>, <64 x i1>, i32) #176 77; Function Attrs: nounwind readnone78declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #179 80; Function Attrs: nounwind readnone81declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #182 83; Function Attrs: nounwind readnone84declare <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32>) #185 86; Function Attrs: nounwind readnone87declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #188 89; Function Attrs: nounwind readnone90declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #191 92attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }93attributes #1 = { nounwind readnone }94 95!0 = !{!1, !1, i64 0}96!1 = !{!"omnipotent char", !2, i64 0}97!2 = !{!"Simple C/C++ TBAA"}98