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1; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s2; Looking for 3rd register field to be restricted to r0-r7.3; v3:2=vdeal(v3,v2,r1)4; CHECK: v{{[0-9]+}}:{{[0-9]+}} = vdeal(v{{[0-9]+}},v{{[0-9]+}},r{{[0-7]+}})5 6target triple = "hexagon"7 8; Function Attrs: nounwind9define void @f0(ptr %a0, i32 %a1, ptr %a2, ptr %a3) #0 {10b0:11 %v0 = alloca ptr, align 412 %v1 = alloca i32, align 413 %v2 = alloca ptr, align 414 %v3 = alloca ptr, align 415 %v4 = alloca i32, align 416 %v5 = alloca i32, align 417 %v6 = alloca i32, align 418 %v7 = alloca i32, align 419 %v8 = alloca i32, align 420 %v9 = alloca ptr, align 421 %v10 = alloca ptr, align 422 %v11 = alloca <16 x i32>, align 6423 %v12 = alloca <16 x i32>, align 6424 %v13 = alloca <32 x i32>, align 12825 %v14 = alloca <16 x i32>, align 6426 %v15 = alloca <16 x i32>, align 6427 %v16 = alloca <32 x i32>, align 12828 %v17 = alloca <16 x i32>, align 6429 %v18 = alloca <16 x i32>, align 6430 store ptr %a0, ptr %v0, align 431 store i32 %a1, ptr %v1, align 432 store ptr %a2, ptr %v2, align 433 store ptr %a3, ptr %v3, align 434 %v19 = load ptr, ptr %v2, align 435 %v20 = getelementptr inbounds i8, ptr %v19, i32 19236 %v22 = load <16 x i32>, ptr %v20, align 6437 store <16 x i32> %v22, ptr %v12, align 6438 store i32 16843009, ptr %v4, align 439 %v23 = load i32, ptr %v4, align 440 %v24 = load i32, ptr %v4, align 441 %v25 = add nsw i32 %v23, %v2442 store i32 %v25, ptr %v5, align 443 %v26 = load i32, ptr %v5, align 444 %v27 = load i32, ptr %v5, align 445 %v28 = add nsw i32 %v26, %v2746 store i32 %v28, ptr %v6, align 447 %v29 = load ptr, ptr %v0, align 448 store ptr %v29, ptr %v9, align 449 %v30 = load ptr, ptr %v3, align 450 store ptr %v30, ptr %v10, align 451 store i32 0, ptr %v8, align 452 br label %b153 54b1: ; preds = %b3, %b055 %v31 = load i32, ptr %v8, align 456 %v32 = load i32, ptr %v1, align 457 %v33 = icmp slt i32 %v31, %v3258 br i1 %v33, label %b2, label %b459 60b2: ; preds = %b161 %v34 = load <16 x i32>, ptr %v11, align 6462 %v35 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v34, i32 -1)63 %v36 = load <16 x i32>, ptr %v14, align 6464 %v37 = load <16 x i32>, ptr %v15, align 6465 %v38 = call <32 x i32> @llvm.hexagon.V6.vswap(<64 x i1> %v35, <16 x i32> %v36, <16 x i32> %v37)66 store <32 x i32> %v38, ptr %v13, align 12867 %v39 = load <32 x i32>, ptr %v13, align 12868 %v40 = call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v39)69 store <16 x i32> %v40, ptr %v14, align 6470 %v41 = load <32 x i32>, ptr %v13, align 12871 %v42 = call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v41)72 store <16 x i32> %v42, ptr %v15, align 6473 %v43 = load <16 x i32>, ptr %v17, align 6474 %v44 = load <16 x i32>, ptr %v18, align 6475 %v45 = load i32, ptr %v7, align 476 %v46 = call <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32> %v43, <16 x i32> %v44, i32 %v45)77 store <32 x i32> %v46, ptr %v16, align 12878 br label %b379 80b3: ; preds = %b281 %v47 = load i32, ptr %v8, align 482 %v48 = add nsw i32 %v47, 183 store i32 %v48, ptr %v8, align 484 br label %b185 86b4: ; preds = %b187 ret void88}89 90; Function Attrs: nounwind readnone91declare <32 x i32> @llvm.hexagon.V6.vswap(<64 x i1>, <16 x i32>, <16 x i32>) #192 93; Function Attrs: nounwind readnone94declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #195 96; Function Attrs: nounwind readnone97declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #198 99; Function Attrs: nounwind readnone100declare <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32>, <16 x i32>, i32) #1101 102; Function Attrs: nounwind readnone103declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1104 105attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }106attributes #1 = { nounwind readnone }107