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1; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s2 3; CHECK: r{{[0-9]*}} += rol(r{{[0-9]*}},#31)4; CHECK: r{{[0-9]*}} &= rol(r{{[0-9]*}},#31)5; CHECK: r{{[0-9]*}} -= rol(r{{[0-9]*}},#31)6; CHECK: r{{[0-9]*}} |= rol(r{{[0-9]*}},#31)7; CHECK: r{{[0-9]*}} ^= rol(r{{[0-9]*}},#31)8 9target triple = "hexagon"10 11@g0 = common global i32 0, align 412@g1 = common global i32 0, align 413@g2 = common global i32 0, align 414@g3 = common global i32 0, align 415@g4 = common global i32 0, align 416 17; Function Attrs: nounwind18define i32 @f0() #0 {19b0:20 %v0 = alloca i32, align 421 %v1 = alloca i32, align 422 store i32 0, ptr %v023 store i32 0, ptr %v1, align 424 %v2 = call i32 @llvm.hexagon.S6.rol.i.r.acc(i32 0, i32 1, i32 31)25 store i32 %v2, ptr @g0, align 426 %v3 = call i32 @llvm.hexagon.S6.rol.i.r.and(i32 0, i32 1, i32 31)27 store i32 %v3, ptr @g1, align 428 %v4 = call i32 @llvm.hexagon.S6.rol.i.r.nac(i32 0, i32 1, i32 31)29 store i32 %v4, ptr @g2, align 430 %v5 = call i32 @llvm.hexagon.S6.rol.i.r.or(i32 0, i32 1, i32 31)31 store i32 %v5, ptr @g3, align 432 %v6 = call i32 @llvm.hexagon.S6.rol.i.r.xacc(i32 0, i32 1, i32 31)33 store i32 %v6, ptr @g4, align 434 ret i32 035}36 37; Function Attrs: nounwind readnone38declare i32 @llvm.hexagon.S6.rol.i.r.acc(i32, i32, i32) #139 40; Function Attrs: nounwind readnone41declare i32 @llvm.hexagon.S6.rol.i.r.and(i32, i32, i32) #142 43; Function Attrs: nounwind readnone44declare i32 @llvm.hexagon.S6.rol.i.r.nac(i32, i32, i32) #145 46; Function Attrs: nounwind readnone47declare i32 @llvm.hexagon.S6.rol.i.r.or(i32, i32, i32) #148 49; Function Attrs: nounwind readnone50declare i32 @llvm.hexagon.S6.rol.i.r.xacc(i32, i32, i32) #151 52attributes #0 = { nounwind "target-cpu"="hexagonv60" }53attributes #1 = { nounwind readnone }54