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1; RUN: llc -mtriple=hexagon -O2 -disable-block-placement < %s | FileCheck %s2; Disable block placement because it intereferes with the generated code.3 4; CHECK:      if (p{{[0-9]*}}) jump:nt .LBB0_25; CHECK-NEXT: v{{[0-9]*}} = vmem(r{{[0-9]*}}+#0)6; CHECK-NEXT: }7 8target triple = "hexagon"9 10@g0 = global <16 x i32> zeroinitializer, align 6411 12; Function Attrs: nounwind13define void @f0(ptr nocapture readonly %a0, i32 %a1, i32 %a2, ptr nocapture %a3) #0 {14b0:15  %v0 = mul i32 %a2, -216  %v1 = add i32 %v0, 6417  %v3 = load <16 x i32>, ptr @g0, align 6418  %v4 = sdiv i32 %a1, 3219  %v5 = icmp sgt i32 %a1, 3120  br i1 %v5, label %b1, label %b421 22b1:                                               ; preds = %b023  %v7 = icmp sgt i32 %a1, 6324  %v8 = mul i32 %v4, 3225  %v9 = select i1 %v7, i32 %v8, i32 3226  %v10 = getelementptr i16, ptr %a3, i32 %v927  br label %b228 29b2:                                               ; preds = %b2, %b130  %v11 = phi i32 [ 0, %b1 ], [ %v19, %b2 ]31  %v12 = phi <16 x i32> [ %v3, %b1 ], [ %v16, %b2 ]32  %v13 = phi ptr [ %a3, %b1 ], [ %v18, %b2 ]33  %v14 = phi ptr [ %a0, %b1 ], [ %v15, %b2 ]34  %v15 = getelementptr inbounds <16 x i32>, ptr %v14, i32 135  %v16 = load <16 x i32>, ptr %v14, align 6436  %v17 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v16, <16 x i32> %v12, i32 %v1)37  %v18 = getelementptr inbounds <16 x i32>, ptr %v13, i32 138  store <16 x i32> %v17, ptr %v13, align 6439  %v19 = add nsw i32 %v11, 140  %v20 = icmp slt i32 %v19, %v441  br i1 %v20, label %b2, label %b342 43b3:                                               ; preds = %b244  %v22 = load <16 x i32>, ptr @g0, align 6445  br label %b446 47b4:                                               ; preds = %b3, %b048  %v23 = phi <16 x i32> [ %v22, %b3 ], [ %v3, %b0 ]49  %v24 = phi <16 x i32> [ %v16, %b3 ], [ %v3, %b0 ]50  %v25 = phi ptr [ %v10, %b3 ], [ %a3, %b0 ]51  %v26 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v23, <16 x i32> %v24, i32 %v1)52  store <16 x i32> %v26, ptr %v25, align 6453  ret void54}55 56; Function Attrs: nounwind readnone57declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #158 59attributes #0 = { nounwind "target-cpu"="hexagonv62" "target-features"="+hvxv62,+hvx-length64b" }60attributes #1 = { nounwind readnone }61