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1; RUN: llc -mtriple=hexagon -disable-hexagon-shuffle=0 -O2 < %s | FileCheck %s2 3; Generate vmemu (unaligned).4; CHECK: vmemu5; CHECK: vmemu6; CHECK: vmemu7; CHECK-NOT: vmem8 9target triple = "hexagon"10 11; Function Attrs: nounwind12define void @f0(ptr nocapture readonly %a0, ptr nocapture readonly %a1, ptr nocapture %a2) #0 {13b0:14 %v1 = load <16 x i32>, ptr %a0, align 4, !tbaa !015 %v3 = load <16 x i32>, ptr %a1, align 4, !tbaa !016 %v4 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %v1, <16 x i32> %v3)17 store <16 x i32> %v4, ptr %a2, align 4, !tbaa !018 ret void19}20 21; Function Attrs: nounwind readnone22declare <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32>, <16 x i32>) #123 24attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }25attributes #1 = { nounwind readnone }26 27!0 = !{!1, !1, i64 0}28!1 = !{!"omnipotent char", !2, i64 0}29!2 = !{!"Simple C/C++ TBAA"}30