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1; RUN: llc -no-integrated-as -mtriple=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s2; RUN: llc -no-integrated-as -mtriple=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s3; generate .long XXXX which is a vector debug print instruction.4; CHECK: .long 0x1dffe05; CHECK: .long 0x1dffe06; CHECK: .long 0x1dffe07; VSTPRINT: .long 0x1dffe08; VSTPRINT-NOT: .long 0x1dffe09target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"10target triple = "hexagon"11 12; Function Attrs: nounwind13define void @do_vecs(ptr nocapture readonly %a, ptr nocapture readonly %b, ptr nocapture %c) #0 {14entry:15 %0 = load <16 x i32>, ptr %a, align 4, !tbaa !116 %1 = load <16 x i32>, ptr %b, align 4, !tbaa !117 %2 = tail call <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32> %0, <16 x i32> %1)18 store <16 x i32> %2, ptr %c, align 4, !tbaa !119 ret void20}21 22; Function Attrs: nounwind readnone23declare <16 x i32> @llvm.hexagon.V6.vaddw(<16 x i32>, <16 x i32>) #124 25attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }26attributes #1 = { nounwind readnone }27 28!llvm.ident = !{!0}29 30!0 = !{!"QuIC LLVM Hexagon Clang version 7.x-pre-unknown"}31!1 = !{!2, !2, i64 0}32!2 = !{!"omnipotent char", !3, i64 0}33!3 = !{!"Simple C/C++ TBAA"}34