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1; RUN: llc -mtriple=hexagon -disable-hexagon-shuffle=1 -O2 < %s | FileCheck %s2; Generate vshuff with 3rd param as an Rt8.3; v1:0=vshuff(v0,v1,r7)4; CHECK: vshuff(v{{[0-9]+}},v{{[0-9]+}},r{{[0-7]}})5 6target triple = "hexagon"7 8@g0 = common global [15 x <16 x i32>] zeroinitializer, align 649@g1 = common global <32 x i32> zeroinitializer, align 12810 11; Function Attrs: nounwind12define i32 @f0() #0 {13b0:14 %v0 = load <16 x i32>, ptr @g0, align 64, !tbaa !015 %v1 = load <16 x i32>, ptr getelementptr inbounds ([15 x <16 x i32>], ptr @g0, i32 0, i32 1), align 64, !tbaa !016 %v2 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> %v0, <16 x i32> %v1, i32 -2147483648)17 store <32 x i32> %v2, ptr @g1, align 128, !tbaa !018 %v3 = tail call i32 @f1(i32 1024, ptr @g1) #019 ret i32 020}21 22; Function Attrs: nounwind readnone23declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #124 25declare i32 @f1(...) #026 27attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }28attributes #1 = { nounwind readnone }29 30!0 = !{!1, !1, i64 0}31!1 = !{!"omnipotent char", !2, i64 0}32!2 = !{!"Simple C/C++ TBAA"}33