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1; RUN: llc -mtriple=hexagon -O2 -enable-pipeliner=false < %s | FileCheck %s2; RUN: llc -mtriple=hexagon -O2 -debug-only=pipeliner < %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-SWP3; REQUIRES: asserts4 5; CHECK: {6; CHECK-DAG: v{{[0-9]*}} = vmem(r{{[0-9]*}}++#1)7; CHECK-DAG: vmem(r{{[0-9]*}}++#1) = v{{[0-9]*}}.new8; CHECK: }{{[ \t]*}}:endloop09 10; CHECK-SWP: Schedule Found? 111; CHECK-SWP: {12; CHECK-DAG-SWP: v{{[0-9]*}}.cur = vmem(r{{[0-9]*}}++#1)13; CHECK-DAG-SWP: vmem(r{{[0-9]*}}++#1) = v{{[0-9]*}}.new14; CHECK-SWP: }{{[ \t]*}}:endloop015 16target triple = "hexagon"17 18; Function Attrs: nounwind19define void @f0(ptr nocapture readonly %a0, i32 %a1, i32 %a2, ptr nocapture %a3) #0 {20b0:21 %v0 = mul i32 %a2, -222 %v1 = add i32 %v0, 6423 %v2 = tail call <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32> undef, <16 x i32> undef)24 %v4 = sdiv i32 %a1, 3225 %v5 = icmp sgt i32 %a1, 3126 br i1 %v5, label %b1, label %b427 28b1: ; preds = %b029 %v7 = icmp sgt i32 %a1, 6330 %v8 = mul i32 %v4, 3231 %v9 = select i1 %v7, i32 %v8, i32 3232 %v10 = getelementptr i16, ptr %a3, i32 %v933 br label %b234 35b2: ; preds = %b2, %b136 %v11 = phi i32 [ 0, %b1 ], [ %v19, %b2 ]37 %v12 = phi <16 x i32> [ %v2, %b1 ], [ %v16, %b2 ]38 %v13 = phi ptr [ %a3, %b1 ], [ %v18, %b2 ]39 %v14 = phi ptr [ %a0, %b1 ], [ %v15, %b2 ]40 %v15 = getelementptr inbounds <16 x i32>, ptr %v14, i32 141 %v16 = load <16 x i32>, ptr %v14, align 64, !tbaa !042 %v17 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v16, <16 x i32> %v12, i32 %v1)43 %v18 = getelementptr inbounds <16 x i32>, ptr %v13, i32 144 store <16 x i32> %v17, ptr %v13, align 64, !tbaa !045 %v19 = add nsw i32 %v11, 146 %v20 = icmp slt i32 %v19, %v447 br i1 %v20, label %b2, label %b348 49b3: ; preds = %b250 br label %b451 52b4: ; preds = %b3, %b053 %v22 = phi <16 x i32> [ %v16, %b3 ], [ %v2, %b0 ]54 %v23 = phi ptr [ %v10, %b3 ], [ %a3, %b0 ]55 %v24 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v2, <16 x i32> %v22, i32 %v1)56 store <16 x i32> %v24, ptr %v23, align 64, !tbaa !057 ret void58}59 60; Function Attrs: nounwind readnone61declare <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32>, <16 x i32>) #162 63; Function Attrs: nounwind readnone64declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #165 66attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }67attributes #1 = { nounwind readnone }68 69!0 = !{!1, !1, i64 0}70!1 = !{!"omnipotent char", !2, i64 0}71!2 = !{!"Simple C/C++ TBAA"}72