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1; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s2; CHECK: vmem3; CHECK: vmem4; CHECK-NOT: r{{[0-9]*}} = add(r30,#-256)5; CHECK: vmem6; CHECK: vmem7 8target triple = "hexagon"9 10; Function Attrs: nounwind11define void @f0(ptr %a0, ptr %a1, i32 %a2, ptr %a3, i32 %a4) #0 {12b0:13 %v0 = alloca ptr, align 414 %v1 = alloca ptr, align 415 %v2 = alloca i32, align 416 %v3 = alloca ptr, align 417 %v4 = alloca i32, align 418 %v5 = alloca <16 x i32>, align 6419 %v6 = alloca <32 x i32>, align 12820 store ptr %a0, ptr %v0, align 421 store ptr %a1, ptr %v1, align 422 store i32 %a2, ptr %v2, align 423 store ptr %a3, ptr %v3, align 424 store i32 %a4, ptr %v4, align 425 %v7 = load ptr, ptr %v0, align 426 %v9 = load <16 x i32>, ptr %v7, align 6427 %v10 = load ptr, ptr %v0, align 428 %v11 = getelementptr inbounds i8, ptr %v10, i32 6429 %v13 = load <16 x i32>, ptr %v11, align 6430 %v14 = call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v9, <16 x i32> %v13)31 store <32 x i32> %v14, ptr %v6, align 12832 %v15 = load ptr, ptr %v3, align 433 %v17 = load <16 x i32>, ptr %v15, align 6434 store <16 x i32> %v17, ptr %v5, align 6435 ret void36}37 38; Function Attrs: nounwind readnone39declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #140 41attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }42attributes #1 = { nounwind readnone }43