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1; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck --check-prefix=CHECKO0 %s2; KP: Removed -O2 check. The code has become more aggressively optimized3; (some loads were found to be redundant and have been removed completely),4; and verifying correct code generation has become more difficult than5; its worth.6 7; CHECK: v{{[0-9]*}} = vsplat(r{{[0-9]*}})8; CHECK: v{{[0-9]*}} = vsplat(r{{[0-9]*}})9 10; CHECKO0: vmem(r{{[0-9]*}}+#0) = v{{[0-9]*}}11; CHECKO0: v{{[0-9]*}} = vmem(r{{[0-9]*}}+#0)12; CHECKO0: v{{[0-9]*}} = vmem(r{{[0-9]*}}+#0)13 14; Allow .cur loads.15; CHECKO2: v{{[0-9].*}} = vmem(r{{[0-9]*}}+#0)16; CHECKO2: vmem(r{{[0-9]*}}+#0) = v{{[0-9]*}}17; CHECKO2: v{{[0-9].*}} = vmem(r{{[0-9]*}}+#0)18 19; CHECK: v{{[0-9]*}}:{{[0-9]*}} = vcombine(v{{[0-9]*}},v{{[0-9]*}})20; CHECK: vmem(r{{[0-9]*}}+#0) = v{{[0-9]*}}21; CHECK: vmem(r{{[0-9]*}}+#32) = v{{[0-9]*}}22; CHECK: v{{[0-9]*}} = vmem(r{{[0-9]*}}+#0)23; CHECK: v{{[0-9]*}} = vmem(r{{[0-9]*}}+#32)24; CHECK: vmem(r{{[0-9]*}}+#0) = v{{[0-9]*}}25; CHECK: vmem(r{{[0-9]*}}+#32) = v{{[0-9]*}}26 27target triple = "hexagon"28 29@g0 = common global [10 x <32 x i32>] zeroinitializer, align 6430@g1 = private unnamed_addr constant [11 x i8] c"c[%d]= %x\0A\00", align 831@g2 = common global [10 x <16 x i32>] zeroinitializer, align 6432@g3 = common global [10 x <16 x i32>] zeroinitializer, align 6433@g4 = common global [10 x <32 x i32>] zeroinitializer, align 6434 35declare i32 @f0(ptr, ...)36 37; Function Attrs: nounwind38define void @f1(i32 %a0) #0 {39b0:40 %v0 = alloca i32, align 441 %v1 = alloca ptr, align 442 %v2 = alloca i32, align 443 store i32 %a0, ptr %v0, align 444 store ptr @g0, ptr %v1, align 445 %v3 = load i32, ptr %v0, align 446 %v4 = load ptr, ptr %v1, align 447 %v5 = getelementptr inbounds i32, ptr %v4, i32 %v348 store ptr %v5, ptr %v1, align 449 store i32 0, ptr %v2, align 450 br label %b151 52b1: ; preds = %b3, %b053 %v6 = load i32, ptr %v2, align 454 %v7 = icmp slt i32 %v6, 1655 br i1 %v7, label %b2, label %b456 57b2: ; preds = %b158 %v8 = load i32, ptr %v2, align 459 %v9 = load ptr, ptr %v1, align 460 %v10 = getelementptr inbounds i32, ptr %v9, i32 161 store ptr %v10, ptr %v1, align 462 %v11 = load i32, ptr %v9, align 463 %v12 = call i32 (ptr, ...) @f0(ptr @g1, i32 %v8, i32 %v11)64 br label %b365 66b3: ; preds = %b267 %v13 = load i32, ptr %v2, align 468 %v14 = add nsw i32 %v13, 169 store i32 %v14, ptr %v2, align 470 br label %b171 72b4: ; preds = %b173 ret void74}75 76; Function Attrs: nounwind77define i32 @f2() #0 {78b0:79 %v0 = alloca i32, align 480 %v1 = alloca i32, align 481 store i32 0, ptr %v082 store i32 0, ptr %v1, align 483 br label %b184 85b1: ; preds = %b3, %b086 %v2 = load i32, ptr %v1, align 487 %v3 = icmp slt i32 %v2, 388 br i1 %v3, label %b2, label %b489 90b2: ; preds = %b191 %v4 = load i32, ptr %v1, align 492 %v5 = add nsw i32 %v4, 193 %v6 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v5)94 %v7 = load i32, ptr %v1, align 495 %v8 = getelementptr inbounds [10 x <16 x i32>], ptr @g2, i32 0, i32 %v796 store <16 x i32> %v6, ptr %v8, align 6497 %v9 = load i32, ptr %v1, align 498 %v10 = mul nsw i32 %v9, 1099 %v11 = add nsw i32 %v10, 1100 %v12 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v11)101 %v13 = load i32, ptr %v1, align 4102 %v14 = getelementptr inbounds [10 x <16 x i32>], ptr @g3, i32 0, i32 %v13103 store <16 x i32> %v12, ptr %v14, align 64104 %v15 = load i32, ptr %v1, align 4105 %v16 = getelementptr inbounds [10 x <16 x i32>], ptr @g2, i32 0, i32 %v15106 %v17 = load <16 x i32>, ptr %v16, align 64107 %v18 = load i32, ptr %v1, align 4108 %v19 = getelementptr inbounds [10 x <16 x i32>], ptr @g3, i32 0, i32 %v18109 %v20 = load <16 x i32>, ptr %v19, align 64110 %v21 = call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v17, <16 x i32> %v20)111 %v22 = load i32, ptr %v1, align 4112 %v23 = getelementptr inbounds [10 x <32 x i32>], ptr @g4, i32 0, i32 %v22113 store <32 x i32> %v21, ptr %v23, align 64114 br label %b3115 116b3: ; preds = %b2117 %v24 = load i32, ptr %v1, align 4118 %v25 = add nsw i32 %v24, 1119 store i32 %v25, ptr %v1, align 4120 br label %b1121 122b4: ; preds = %b1123 store i32 0, ptr %v1, align 4124 br label %b5125 126b5: ; preds = %b7, %b4127 %v26 = load i32, ptr %v1, align 4128 %v27 = icmp slt i32 %v26, 3129 br i1 %v27, label %b6, label %b8130 131b6: ; preds = %b5132 %v28 = load i32, ptr %v1, align 4133 %v29 = getelementptr inbounds [10 x <32 x i32>], ptr @g4, i32 0, i32 %v28134 %v30 = load <32 x i32>, ptr %v29, align 64135 %v31 = load i32, ptr %v1, align 4136 %v32 = getelementptr inbounds [10 x <32 x i32>], ptr @g0, i32 0, i32 %v31137 store <32 x i32> %v30, ptr %v32, align 64138 br label %b7139 140b7: ; preds = %b6141 %v33 = load i32, ptr %v1, align 4142 %v34 = add nsw i32 %v33, 1143 store i32 %v34, ptr %v1, align 4144 br label %b5145 146b8: ; preds = %b5147 store i32 0, ptr %v1, align 4148 br label %b9149 150b9: ; preds = %b11, %b8151 %v35 = load i32, ptr %v1, align 4152 %v36 = icmp slt i32 %v35, 3153 br i1 %v36, label %b10, label %b12154 155b10: ; preds = %b9156 %v37 = load i32, ptr %v1, align 4157 %v38 = mul nsw i32 %v37, 16158 call void @f1(i32 %v38)159 br label %b11160 161b11: ; preds = %b10162 %v39 = load i32, ptr %v1, align 4163 %v40 = add nsw i32 %v39, 1164 store i32 %v40, ptr %v1, align 4165 br label %b9166 167b12: ; preds = %b9168 ret i32 0169}170 171; Function Attrs: nounwind readnone172declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1173 174; Function Attrs: nounwind readnone175declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1176 177attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }178attributes #1 = { nounwind readnone }179