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1; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s2; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s3; RUN: llc -mtriple=hexagon -O1 < %s | FileCheck %s4; RUN: llc -mtriple=hexagon -O0 < %s | FileCheck %s5;6; CHECK-NOT: v{{[0-9]*}}.cur7;8; CHECK: {9; CHECK: v{{[0-9]+}}.h = vasr(v{{[0-9]+}}.w,v{{[0-9]+}}.w,r{{[0-7]+}})10 11; CHECK: }12; CHECK: {13; CHECK: v{{[0-9]+}}.h = vasr(v{{[0-9]+}}.w,v{{[0-9]+}}.w,r{{[0-7]+}})14; CHECK: }15; CHECK-NOT: vand16; CHECK: v{{[0-9]+}} = v{{[0-9]+}}17 18target triple = "hexagon"19 20; Function Attrs: nounwind21define void @f0(ptr nocapture readonly %a0, ptr nocapture readonly %a1, i32 %a2, ptr nocapture %a3, i32 %a4) #0 {22b0:23 %v1 = load i32, ptr %a1, align 4, !tbaa !024 %v2 = getelementptr inbounds i8, ptr %a1, i32 425 %v4 = load i32, ptr %v2, align 4, !tbaa !026 %v5 = getelementptr inbounds i8, ptr %a1, i32 827 %v7 = load i32, ptr %v5, align 4, !tbaa !028 %v8 = mul i32 %a4, 229 %v9 = add i32 %v8, %a430 %v10 = icmp sgt i32 %a4, 031 br i1 %v10, label %b1, label %b432 33b1: ; preds = %b034 %v11 = getelementptr inbounds i8, ptr %a0, i32 %v935 %v12 = getelementptr inbounds i8, ptr %a0, i32 %v836 %v13 = getelementptr inbounds i8, ptr %a0, i32 %a437 %v14 = add i32 %v9, 6438 %v16 = add i32 %v8, 6439 %v18 = add i32 %a4, 6440 %v21 = getelementptr inbounds i8, ptr %a0, i32 %v1441 %v22 = load <16 x i32>, ptr %v11, align 64, !tbaa !442 %v23 = getelementptr inbounds i8, ptr %a0, i32 %v1643 %v24 = load <16 x i32>, ptr %v12, align 64, !tbaa !444 %v25 = getelementptr inbounds i8, ptr %a0, i32 %v1845 %v26 = load <16 x i32>, ptr %v13, align 64, !tbaa !446 %v27 = load <16 x i32>, ptr %a0, align 64, !tbaa !447 %v28 = getelementptr inbounds i8, ptr %a3, i32 %a448 br label %b249 50b2: ; preds = %b2, %b151 %v29 = phi ptr [ %a0, %b1 ], [ %v40, %b2 ]52 %v30 = phi ptr [ %a3, %b1 ], [ %v74, %b2 ]53 %v31 = phi ptr [ %v25, %b1 ], [ %v45, %b2 ]54 %v32 = phi ptr [ %v23, %b1 ], [ %v48, %b2 ]55 %v33 = phi ptr [ %v21, %b1 ], [ %v51, %b2 ]56 %v34 = phi ptr [ %v28, %b1 ], [ %v89, %b2 ]57 %v35 = phi i32 [ 0, %b1 ], [ %v90, %b2 ]58 %v36 = phi <16 x i32> [ %v27, %b1 ], [ %v42, %b2 ]59 %v37 = phi <16 x i32> [ %v26, %b1 ], [ %v44, %b2 ]60 %v38 = phi <16 x i32> [ %v24, %b1 ], [ %v47, %b2 ]61 %v39 = phi <16 x i32> [ %v22, %b1 ], [ %v50, %b2 ]62 %v40 = getelementptr inbounds i8, ptr %v29, i32 6463 %v42 = load <16 x i32>, ptr %v40, align 64, !tbaa !464 %v44 = load <16 x i32>, ptr %v31, align 64, !tbaa !465 %v45 = getelementptr inbounds i8, ptr %v31, i32 6466 %v47 = load <16 x i32>, ptr %v32, align 64, !tbaa !467 %v48 = getelementptr inbounds i8, ptr %v32, i32 6468 %v50 = load <16 x i32>, ptr %v33, align 64, !tbaa !469 %v51 = getelementptr inbounds i8, ptr %v33, i32 6470 %v52 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v42, <16 x i32> %v36, i32 4)71 %v53 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v44, <16 x i32> %v37, i32 4)72 %v54 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v47, <16 x i32> %v38, i32 4)73 %v55 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v50, <16 x i32> %v39, i32 4)74 %v56 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v52, <16 x i32> %v36)75 %v57 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v53, <16 x i32> %v37)76 %v58 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v54, <16 x i32> %v38)77 %v59 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v55, <16 x i32> %v39)78 %v60 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v56, i32 %v1, i32 0)79 %v61 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v56, i32 %v1, i32 1)80 %v62 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v60, <32 x i32> %v57, i32 %v4, i32 0)81 %v63 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v61, <32 x i32> %v57, i32 %v4, i32 1)82 %v64 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v62, <32 x i32> %v58, i32 %v7, i32 0)83 %v65 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v63, <32 x i32> %v58, i32 %v7, i32 1)84 %v66 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v65)85 %v67 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v65)86 %v68 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %v66, <16 x i32> %v67, i32 %a2)87 %v69 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v64)88 %v70 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v64)89 %v71 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %v69, <16 x i32> %v70, i32 %a2)90 %v72 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v68, <16 x i32> %v71)91 store <16 x i32> %v72, ptr %v30, align 64, !tbaa !492 %v74 = getelementptr inbounds i8, ptr %v30, i32 6493 %v75 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v57, i32 %v1, i32 0)94 %v76 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v57, i32 %v1, i32 1)95 %v77 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v75, <32 x i32> %v58, i32 %v4, i32 0)96 %v78 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v76, <32 x i32> %v58, i32 %v4, i32 1)97 %v79 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v77, <32 x i32> %v59, i32 %v7, i32 0)98 %v80 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %v78, <32 x i32> %v59, i32 %v7, i32 1)99 %v81 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v80)100 %v82 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v80)101 %v83 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %v81, <16 x i32> %v82, i32 %a2)102 %v84 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v79)103 %v85 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v79)104 %v86 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %v84, <16 x i32> %v85, i32 %a2)105 %v87 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v83, <16 x i32> %v86)106 store <16 x i32> %v87, ptr %v34, align 64, !tbaa !4107 %v89 = getelementptr inbounds i8, ptr %v34, i32 64108 %v90 = add nsw i32 %v35, 64109 %v91 = icmp slt i32 %v90, %a4110 br i1 %v91, label %b2, label %b3111 112b3: ; preds = %b2113 br label %b4114 115b4: ; preds = %b3, %b0116 ret void117}118 119; Function Attrs: nounwind readnone120declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1121 122; Function Attrs: nounwind readnone123declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1124 125; Function Attrs: nounwind readnone126declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #1127 128; Function Attrs: nounwind readnone129declare <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32>, <32 x i32>, i32, i32) #1130 131; Function Attrs: nounwind readnone132declare <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32>, <16 x i32>, i32) #1133 134; Function Attrs: nounwind readnone135declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1136 137; Function Attrs: nounwind readnone138declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1139 140; Function Attrs: nounwind readnone141declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1142 143attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }144attributes #1 = { nounwind readnone }145 146!0 = !{!1, !1, i64 0}147!1 = !{!"int", !2, i64 0}148!2 = !{!"omnipotent char", !3, i64 0}149!3 = !{!"Simple C/C++ TBAA"}150!4 = !{!2, !2, i64 0}151