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1; RUN: llc -mtriple=hexagon -enable-pipeliner=false -hexagon-vector-combine=false < %s | FileCheck %s2 3; Test that the vsplat and vmemu are not all serialized due to chain edges4; caused by the hasSideEffects flag. The exact code generation may change5; due to the scheduling changes, but we shouldn't see a series of6; vsplat and vmemu instructions that each occur in a single packet.7 8; CHECK: loop0(.LBB0_[[LOOP:.]],9; CHECK: .LBB0_[[LOOP]]:10; CHECK: vsplat11; CHECK-NEXT: vsplat12; CHECK: vsplat13; CHECK-NEXT: vsplat14; CHECK: endloop015 16@g0 = global [256 x i8] c"^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^00226644,,..**8888::66,,,,&&^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^22000022..4444>>::8888**..^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^<<66220000226644<<>>::^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^>><<446622000022>>", align 6417 18; Function Attrs: nounwind19define void @f0(ptr noalias nocapture readonly %a0, ptr noalias nocapture readonly %a1, ptr noalias nocapture %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6) #0 {20b0:21 %v0 = load <16 x i32>, ptr @g0, align 64, !tbaa !022 %v1 = load <16 x i32>, ptr getelementptr inbounds ([256 x i8], ptr @g0, i32 0, i32 64), align 64, !tbaa !023 %v2 = load <16 x i32>, ptr getelementptr inbounds ([256 x i8], ptr @g0, i32 0, i32 128), align 64, !tbaa !024 %v3 = load <16 x i32>, ptr getelementptr inbounds ([256 x i8], ptr @g0, i32 0, i32 192), align 64, !tbaa !025 %v4 = icmp sgt i32 %a5, 026 br i1 %v4, label %b1, label %b527 28b1: ; preds = %b029 %v6 = tail call <16 x i32> @llvm.hexagon.V6.vd0()30 %v8 = mul nsw i32 %a3, 431 %v9 = add i32 %v8, %a632 %v10 = add i32 %v9, 3233 %v11 = add i32 %a5, -134 br label %b235 36b2: ; preds = %b4, %b137 %v12 = phi i32 [ 0, %b1 ], [ %v59, %b4 ]38 %v13 = phi ptr [ %a2, %b1 ], [ %v58, %b4 ]39 %v14 = getelementptr ptr, ptr %a0, i32 %v1240 br label %b341 42b3: ; preds = %b3, %b243 %v15 = phi ptr [ %v14, %b2 ], [ %v57, %b3 ]44 %v16 = phi i32 [ 0, %b2 ], [ %v55, %b3 ]45 %v17 = phi ptr [ %a1, %b2 ], [ %v23, %b3 ]46 %v18 = phi <16 x i32> [ %v6, %b2 ], [ %v54, %b3 ]47 %v19 = load ptr, ptr %v15, align 4, !tbaa !348 %v20 = getelementptr inbounds i16, ptr %v19, i32 %v949 %v21 = getelementptr inbounds i64, ptr %v17, i32 150 %v22 = load i64, ptr %v17, align 8, !tbaa !051 %v23 = getelementptr inbounds i64, ptr %v17, i32 252 %v24 = load i64, ptr %v21, align 8, !tbaa !053 %v25 = trunc i64 %v22 to i3254 %v26 = lshr i64 %v22, 3255 %v27 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v25)56 %v28 = trunc i64 %v26 to i3257 %v29 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v28)58 %v30 = trunc i64 %v24 to i3259 %v31 = lshr i64 %v24, 3260 %v32 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v30)61 %v33 = trunc i64 %v31 to i3262 %v34 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v33)63 %v36 = load <16 x i32>, ptr %v20, align 4, !tbaa !064 %v37 = getelementptr inbounds i16, ptr %v19, i32 %v1065 %v39 = load <16 x i32>, ptr %v37, align 4, !tbaa !066 %v40 = tail call <16 x i32> @llvm.hexagon.V6.vpackeh(<16 x i32> %v39, <16 x i32> %v36)67 %v41 = tail call <16 x i32> @llvm.hexagon.V6.vpackeh(<16 x i32> %v40, <16 x i32> %v40)68 %v42 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %v41, <16 x i32> %v0)69 %v43 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %v41, <16 x i32> %v1)70 %v44 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %v41, <16 x i32> %v2)71 %v45 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %v41, <16 x i32> %v3)72 %v46 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v27, <16 x i32> %v42)73 %v47 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v29, <16 x i32> %v43)74 %v48 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v32, <16 x i32> %v44)75 %v49 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v34, <16 x i32> %v45)76 %v50 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat(<16 x i32> %v46, <16 x i32> %v46)77 %v51 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32> %v50, <16 x i32> %v47, <16 x i32> %v47)78 %v52 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32> %v51, <16 x i32> %v48, <16 x i32> %v48)79 %v53 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32> %v52, <16 x i32> %v49, <16 x i32> %v49)80 %v54 = tail call <16 x i32> @llvm.hexagon.V6.vasrw.acc(<16 x i32> %v18, <16 x i32> %v53, i32 6)81 %v55 = add nsw i32 %v16, 182 %v56 = icmp eq i32 %v16, 783 %v57 = getelementptr ptr, ptr %v15, i32 184 br i1 %v56, label %b4, label %b385 86b4: ; preds = %b387 %v58 = getelementptr inbounds <16 x i32>, ptr %v13, i32 188 store <16 x i32> %v54, ptr %v13, align 64, !tbaa !089 %v59 = add nsw i32 %v12, 190 %v60 = icmp eq i32 %v12, %v1191 br i1 %v60, label %b5, label %b292 93b5: ; preds = %b4, %b094 ret void95}96 97; Function Attrs: nounwind readnone98declare <16 x i32> @llvm.hexagon.V6.vd0() #199 100; Function Attrs: nounwind readnone101declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1102 103; Function Attrs: nounwind readnone104declare <16 x i32> @llvm.hexagon.V6.vpackeh(<16 x i32>, <16 x i32>) #1105 106; Function Attrs: nounwind readnone107declare <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32>, <16 x i32>) #1108 109; Function Attrs: nounwind readnone110declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #1111 112; Function Attrs: nounwind readnone113declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat(<16 x i32>, <16 x i32>) #1114 115; Function Attrs: nounwind readnone116declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32>, <16 x i32>, <16 x i32>) #1117 118; Function Attrs: nounwind readnone119declare <16 x i32> @llvm.hexagon.V6.vasrw.acc(<16 x i32>, <16 x i32>, i32) #1120 121attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }122attributes #1 = { nounwind readnone }123 124!0 = !{!1, !1, i64 0}125!1 = !{!"omnipotent char", !2, i64 0}126!2 = !{!"Simple C/C++ TBAA"}127!3 = !{!4, !4, i64 0}128!4 = !{!"any pointer", !1, i64 0}129