43 lines · plain
1; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s2; CHECK-DAG: v{{[0-9]+}} = vsplat(r{{[0-9]+}})3; CHECK-DAG: v{{[0-9]+}} = vsplat(r{{[0-9]+}})4; CHECK-DAG: q{{[0-3]}} = vand(v{{[0-9]+}},r{{[0-9]+}})5; CHECK: v{{[0-9]+}} = vmux(q{{[0-3]}},v{{[0-9]+}},v{{[0-9]+}})6 7target triple = "hexagon"8 9@g0 = common global <16 x i32> zeroinitializer, align 6410@g1 = common global <16 x i32> zeroinitializer, align 6411@g2 = common global <16 x i32> zeroinitializer, align 6412@g3 = common global <16 x i32> zeroinitializer, align 6413 14; Function Attrs: nounwind15define i32 @f0() #0 {16b0:17 %v0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 11)18 store <16 x i32> %v0, ptr @g1, align 64, !tbaa !019 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 12)20 store <16 x i32> %v1, ptr @g2, align 64, !tbaa !021 %v2 = load <16 x i32>, ptr @g0, align 64, !tbaa !022 %v3 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v2, i32 -1)23 %v4 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v3, <16 x i32> %v0, <16 x i32> %v1)24 store <16 x i32> %v4, ptr @g3, align 64, !tbaa !025 ret i32 026}27 28; Function Attrs: nounwind readnone29declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #130 31; Function Attrs: nounwind readnone32declare <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1>, <16 x i32>, <16 x i32>) #133 34; Function Attrs: nounwind readnone35declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #136 37attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }38attributes #1 = { nounwind readnone }39 40!0 = !{!1, !1, i64 0}41!1 = !{!"omnipotent char", !2}42!2 = !{!"Simple C/C++ TBAA"}43