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1; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s2; CHECK-NOT: vsplat3; CHECK: call f24; CHECK: v{{[0-9]+}} = vsplat5; CHECK: v{{[0-9]+}} = vsplat6; CHECK: v{{[0-9]+}} = vsplat7; CHECK: v{{[0-9]+}} = vsplat8 9target triple = "hexagon"10 11@g0 = common global [2 x <32 x i32>] zeroinitializer, align 12812@g1 = common global <32 x i32> zeroinitializer, align 12813@g2 = common global [2 x <16 x i32>] zeroinitializer, align 6414 15; Function Attrs: nounwind16define i32 @f0() #0 {17b0:18 tail call void @f1() #219 %v0 = tail call i32 @f2(i8 zeroext 0) #220 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) #221 store <16 x i32> %v1, ptr @g2, align 64, !tbaa !022 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2) #223 store <16 x i32> %v2, ptr getelementptr inbounds ([2 x <16 x i32>], ptr @g2, i32 0, i32 1), align 64, !tbaa !024 %v3 = tail call <32 x i32> @llvm.hexagon.V6.vaddubh(<16 x i32> %v1, <16 x i32> %v2) #225 store <32 x i32> %v3, ptr @g0, align 128, !tbaa !026 store <32 x i32> %v3, ptr getelementptr inbounds ([2 x <32 x i32>], ptr @g0, i32 0, i32 1), align 128, !tbaa !027 %v4 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v3, <32 x i32> %v3, i32 -2147483648)28 store <32 x i32> %v4, ptr @g1, align 128, !tbaa !029 ret i32 030}31 32declare void @f1() #033 34declare i32 @f2(i8 zeroext) #035 36; Function Attrs: nounwind readnone37declare <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32>, <32 x i32>, i32) #138 39; Function Attrs: nounwind40define void @f3() #0 {41b0:42 %v0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)43 store <16 x i32> %v0, ptr @g2, align 64, !tbaa !044 %v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2)45 store <16 x i32> %v1, ptr getelementptr inbounds ([2 x <16 x i32>], ptr @g2, i32 0, i32 1), align 64, !tbaa !046 %v2 = tail call <32 x i32> @llvm.hexagon.V6.vaddubh(<16 x i32> %v0, <16 x i32> %v1)47 store <32 x i32> %v2, ptr @g0, align 128, !tbaa !048 store <32 x i32> %v2, ptr getelementptr inbounds ([2 x <32 x i32>], ptr @g0, i32 0, i32 1), align 128, !tbaa !049 ret void50}51 52; Function Attrs: nounwind readnone53declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #154 55; Function Attrs: nounwind readnone56declare <32 x i32> @llvm.hexagon.V6.vaddubh(<16 x i32>, <16 x i32>) #157 58attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }59attributes #1 = { nounwind readnone }60attributes #2 = { nounwind }61 62!0 = !{!1, !1, i64 0}63!1 = !{!"omnipotent char", !2, i64 0}64!2 = !{!"Simple C/C++ TBAA"}65