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1; RUN: llc -mtriple=hexagon -O0 < %s2 3; This is a regression test which makes sure that the offset check4; is available for STRiw_indexed instruction. This is required5; by 'Hexagon Expand Predicate Spill Code' pass.6 7define i32 @f0(i32 %a0, i32 %a1) #0 {8b0:9 %v0 = alloca i32, align 410 %v1 = alloca i32, align 411 %v2 = alloca i32, align 412 store i32 %a0, ptr %v1, align 413 store i32 %a1, ptr %v2, align 414 %v3 = load i32, ptr %v1, align 415 %v4 = load i32, ptr %v2, align 416 %v5 = icmp sgt i32 %v3, %v417 br i1 %v5, label %b1, label %b218 19b1: ; preds = %b020 %v6 = load i32, ptr %v1, align 421 %v7 = load i32, ptr %v2, align 422 %v8 = add nsw i32 %v6, %v723 store i32 %v8, ptr %v024 br label %b325 26b2: ; preds = %b027 %v9 = load i32, ptr %v1, align 428 %v10 = load i32, ptr %v2, align 429 %v11 = sub nsw i32 %v9, %v1030 store i32 %v11, ptr %v031 br label %b332 33b3: ; preds = %b2, %b134 %v12 = load i32, ptr %v035 ret i32 %v1236}37 38attributes #0 = { nounwind "target-cpu"="hexagonv5" }39