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1; RUN: llc -mtriple=hexagon < %s2; REQUIRES: asserts3; Check that llc does not crash.4 5@g0 = private unnamed_addr constant [7 x i8] c"%d\09\09%d\00", align 16@g1 = common global <4 x i32> zeroinitializer, align 167 8declare i32 @f0(...)9 10; Function Attrs: nounwind11define i32 @f1() #0 {12b0:13 %v0 = alloca i32, align 414 %v1 = alloca i32, align 415 %v2 = alloca [0 x <4 x i32>], align 1616 store i32 0, ptr %v017 store i32 0, ptr %v1, align 418 call void @llvm.memset.p0.i32(ptr align 16 %v2, i8 0, i32 0, i1 false)19 %v4 = load i32, ptr %v1, align 420 %v5 = add nsw i32 %v4, 121 store i32 %v5, ptr %v1, align 422 %v6 = load <4 x i32>, ptr @g1, align 1623 %v7 = call i32 @f0(ptr @g0, i32 %v5, <4 x i32> %v6)24 ret i32 025}26 27; Function Attrs: argmemonly nounwind28declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1) #129 30attributes #0 = { nounwind "target-cpu"="hexagonv60" }31attributes #1 = { argmemonly nounwind }32