56 lines · plain
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; This testcase is known to generate an opportunity for creating vcombine4; in HexagonCopyToCombine.5 6; CHECK: vcombine7 8target triple = "hexagon-unknown--elf"9 10declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #011declare <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32>, <32 x i32>) #012declare <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32>, <32 x i32>, i32) #013declare <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32>, <32 x i32>) #014declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #015declare <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32>, <64 x i32>) #016declare <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32>, <32 x i32>) #017declare <64 x i32> @llvm.hexagon.V6.vmpyub.128B(<32 x i32>, i32) #018 19define void @f0(ptr %a0, ptr %a1) local_unnamed_addr #1 {20b0:21 %v0 = load <32 x i32>, ptr %a0, align 12822 %v1 = load <32 x i32>, ptr %a1, align 12823 br i1 undef, label %b2, label %b124 25b1: ; preds = %b026 %v2 = tail call <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32> %v0, <32 x i32> %v1, i32 1)27 %v3 = tail call <64 x i32> @llvm.hexagon.V6.vmpyub.128B(<32 x i32> %v2, i32 33686018) #128 %v4 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %v3) #129 %v5 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v4)30 %v6 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> %v5, <32 x i32> undef) #131 %v7 = tail call <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32> %v6, <32 x i32> undef)32 %v8 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %v7) #133 %v9 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v8) #134 %v10 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %v9, <32 x i32> undef) #135 store <32 x i32> %v10, ptr %a0, align 12836 br label %b237 38b2: ; preds = %b1, %b039 %v11 = phi <32 x i32> [ zeroinitializer, %b1 ], [ %v0, %b0 ]40 %v12 = phi <32 x i32> [ %v0, %b1 ], [ %v1, %b0 ]41 %v13 = tail call <32 x i32> @llvm.hexagon.V6.vlalignbi.128B(<32 x i32> %v11, <32 x i32> %v12, i32 1)42 %v14 = tail call <64 x i32> @llvm.hexagon.V6.vmpyub.128B(<32 x i32> %v13, i32 33686018) #143 %v15 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %v14) #144 %v16 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v15)45 %v17 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> %v16, <32 x i32> undef) #146 %v18 = tail call <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32> %v17, <32 x i32> undef)47 %v19 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %v18) #148 %v20 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v19) #149 %v21 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %v20, <32 x i32> undef) #150 store <32 x i32> %v21, ptr %a1, align 12851 ret void52}53 54attributes #0 = { nounwind readnone }55attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }56