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1; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s2 3; Test that we convert 128B vcombine instructions to REG_SEQUENCE instructions.4 5; CHECK-LABEL: f0:6; CHECK-NOT: vcombine7define void @f0(ptr nocapture readonly %a0, ptr nocapture readonly %a1, i32 %a2, ptr nocapture %a3, i32 %a4, i32 %a5) #0 {8b0:9 %v1 = load i64, ptr %a1, align 810 %v2 = shl i64 %v1, 811 %v3 = trunc i64 %v2 to i3212 %v4 = trunc i64 %v1 to i3213 %v5 = and i32 %v4, 1677721514 %v7 = load <32 x i32>, ptr %a0, align 12815 %v8 = getelementptr inbounds i8, ptr %a0, i32 3216 %v10 = load <32 x i32>, ptr %v8, align 12817 %v11 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %v10, <32 x i32> %v7)18 %v12 = tail call <64 x i32> @llvm.hexagon.V6.vrmpybusi.128B(<64 x i32> %v11, i32 %v5, i32 0)19 %v13 = tail call <64 x i32> @llvm.hexagon.V6.vrmpybusi.128B(<64 x i32> %v11, i32 %v3, i32 0)20 %v14 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v12)21 %v15 = tail call <32 x i32> @llvm.hexagon.V6.vasrwuhsat.128B(<32 x i32> %v14, <32 x i32> %v14, i32 %a2)22 %v16 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v13)23 %v17 = tail call <32 x i32> @llvm.hexagon.V6.vasrwuhsat.128B(<32 x i32> %v16, <32 x i32> %v16, i32 %a2)24 %v18 = getelementptr inbounds i8, ptr %a3, i32 3225 store <32 x i32> %v15, ptr %v18, align 12826 store <32 x i32> %v17, ptr %a3, align 12827 ret void28}29 30; CHECK-LABEL: f1:31; CHECK-NOT: vcombine32define void @f1() #0 {33b0:34 br i1 undef, label %b1, label %b335 36b1: ; preds = %b1, %b037 %v0 = phi <64 x i32> [ %v6, %b1 ], [ undef, %b0 ]38 %v1 = tail call <64 x i32> @llvm.hexagon.V6.vmpybus.acc.128B(<64 x i32> %v0, <32 x i32> undef, i32 16843009)39 %v2 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %v1, <64 x i32> undef, i32 16843009)40 %v3 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %v2, <64 x i32> undef, i32 16843009)41 %v4 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %v3, <64 x i32> undef, i32 16843009)42 %v5 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> undef, <32 x i32> undef)43 %v6 = tail call <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32> %v4, <64 x i32> %v5, i32 16843009)44 br i1 false, label %b2, label %b145 46b2: ; preds = %b147 %v7 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v6)48 unreachable49 50b3: ; preds = %b051 ret void52}53 54; Function Attrs: nounwind readnone55declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #156 57; Function Attrs: nounwind readnone58declare <64 x i32> @llvm.hexagon.V6.vrmpybusi.128B(<64 x i32>, i32, i32) #159 60; Function Attrs: nounwind readnone61declare <32 x i32> @llvm.hexagon.V6.vasrwuhsat.128B(<32 x i32>, <32 x i32>, i32) #162 63; Function Attrs: nounwind readnone64declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #165 66; Function Attrs: nounwind readnone67declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #168 69; Function Attrs: nounwind readnone70declare <64 x i32> @llvm.hexagon.V6.vmpybus.acc.128B(<64 x i32>, <32 x i32>, i32) #171 72; Function Attrs: nounwind readnone73declare <64 x i32> @llvm.hexagon.V6.vmpabus.acc.128B(<64 x i32>, <64 x i32>, i32) #174 75attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }76attributes #1 = { nounwind readnone }77