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1; RUN: llc -mtriple=hexagon < %s2; REQUIRES: asserts3 4target triple = "hexagon"5 6@g0 = common global <16 x i32> zeroinitializer, align 647@g1 = common global <32 x i32> zeroinitializer, align 1288@g2 = common global <32 x i32> zeroinitializer, align 1289 10; Function Attrs: nounwind11define void @f0() #0 {12b0:13 %v0 = load <16 x i32>, ptr @g0, align 6414 %v1 = load <32 x i32>, ptr @g1, align 12815 %v2 = call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v1)16 %v3 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v0, <16 x i32> %v2)17 store <32 x i32> %v3, ptr @g2, align 12818 ret void19}20 21; Function Attrs: nounwind readnone22declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #123 24; Function Attrs: nounwind readnone25declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #126 27attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }28attributes #1 = { nounwind readnone }29