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1; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s2; CHECK-NOT: vcombine3 4define void @f0(ptr nocapture readonly %a0, ptr nocapture readonly %a1, i32 %a2, ptr nocapture %a3, i32 %a4, i32 %a5) #0 {5b0:6 %v1 = load i64, ptr %a1, align 87 %v2 = shl i64 %v1, 88 %v3 = trunc i64 %v2 to i329 %v4 = trunc i64 %v1 to i3210 %v5 = and i32 %v4, 1677721511 %v7 = load <16 x i32>, ptr %a0, align 6412 %v8 = getelementptr inbounds i8, ptr %a0, i32 3213 %v10 = load <16 x i32>, ptr %v8, align 6414 %v11 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v10, <16 x i32> %v7)15 %v12 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v11, i32 %v5, i32 0)16 %v13 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %v11, i32 %v3, i32 0)17 %v14 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v12)18 %v15 = tail call <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32> %v14, <16 x i32> %v14, i32 %a2)19 %v16 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v13)20 %v17 = tail call <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32> %v16, <16 x i32> %v16, i32 %a2)21 %v18 = getelementptr inbounds i8, ptr %a3, i32 3222 store <16 x i32> %v15, ptr %v18, align 6423 store <16 x i32> %v17, ptr %a3, align 6424 ret void25}26 27; Function Attrs: nounwind readnone28declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #129 30; Function Attrs: nounwind readnone31declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #132 33; Function Attrs: nounwind readnone34declare <16 x i32> @llvm.hexagon.V6.vasrwuhsat(<16 x i32>, <16 x i32>, i32) #135 36; Function Attrs: nounwind readnone37declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #138 39; Function Attrs: nounwind readnone40declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #141 42attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }43attributes #1 = { nounwind readnone }44