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1; RUN: llc -mtriple=hexagon -mcpu=hexagonv60 -O2 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s2 3; CHECK: vmem(r{{[0-9]+}}+#3) = v{{[0-9]+}}4; CHECK: call puts5; CHECK: call print_vecpred6; CHECK: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#3)7 8target triple = "hexagon"9 10@K = global i64 0, align 811@src = global i32 -1, align 412@Q6VecPredResult = common global <16 x i32> zeroinitializer, align 6413@dst_addresses = common global [15 x i64] zeroinitializer, align 814@ptr_addresses = common global [15 x ptr] zeroinitializer, align 815@src_addresses = common global [15 x ptr] zeroinitializer, align 816@ptr = common global [32768 x i32] zeroinitializer, align 817@vecpreds = common global [15 x <16 x i32>] zeroinitializer, align 6418@VectorResult = common global <16 x i32> zeroinitializer, align 6419@vectors = common global [15 x <16 x i32>] zeroinitializer, align 6420@VectorPairResult = common global <32 x i32> zeroinitializer, align 12821@vector_pairs = common global [15 x <32 x i32>] zeroinitializer, align 12822@str = private unnamed_addr constant [106 x i8] c"Q6VecPred4 : Q6_Q_vandor_QVR(Q6_Q_vand_VR(Q6_V_vsplat_R(1+1),(0x01010101)),Q6_V_vsplat_R(0+1),INT32_MIN)\00"23@str3 = private unnamed_addr constant [99 x i8] c"Q6VecPred4 : Q6_Q_vandor_QVR(Q6_Q_vand_VR(Q6_V_vsplat_R(1+1),(0x01010101)),Q6_V_vsplat_R(0+1),-1)\00"24@str4 = private unnamed_addr constant [98 x i8] c"Q6VecPred4 : Q6_Q_vandor_QVR(Q6_Q_vand_VR(Q6_V_vsplat_R(1+1),(0x01010101)),Q6_V_vsplat_R(0+1),0)\00"25 26; Function Attrs: nounwind27define i32 @main() #0 {28entry:29 %call = tail call i32 @init_addresses() #330 %call1 = tail call i32 @acquire_vector_unit(i8 zeroext 0) #331 tail call void @init_vectors() #332 %0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2)33 %1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %0, i32 16843009)34 %2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)35 %3 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt.acc(<64 x i1> %1, <16 x i32> %2, i32 -2147483648)36 %4 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %3, i32 -1)37 store <16 x i32> %4, ptr @Q6VecPredResult, align 64, !tbaa !138 %puts = tail call i32 @puts(ptr @str)39 tail call void @print_vecpred(i32 512, ptr @Q6VecPredResult) #340 %5 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt.acc(<64 x i1> %1, <16 x i32> %2, i32 -1)41 %6 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %5, i32 -1)42 store <16 x i32> %6, ptr @Q6VecPredResult, align 64, !tbaa !143 %puts5 = tail call i32 @puts(ptr @str3)44 tail call void @print_vecpred(i32 512, ptr @Q6VecPredResult) #345 %7 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt.acc(<64 x i1> %1, <16 x i32> %2, i32 0)46 %8 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %7, i32 -1)47 store <16 x i32> %8, ptr @Q6VecPredResult, align 64, !tbaa !148 %puts6 = tail call i32 @puts(ptr @str4)49 tail call void @print_vecpred(i32 512, ptr @Q6VecPredResult) #350 ret i32 051}52 53declare i32 @init_addresses(...) #154 55declare i32 @acquire_vector_unit(i8 zeroext) #156 57declare void @init_vectors() #158 59; Function Attrs: nounwind readnone60declare <64 x i1> @llvm.hexagon.V6.vandvrt.acc(<64 x i1>, <16 x i32>, i32) #261 62; Function Attrs: nounwind readnone63declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #264 65; Function Attrs: nounwind readnone66declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #267 68; Function Attrs: nounwind readnone69declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #270 71declare void @print_vecpred(i32, ptr) #172 73; Function Attrs: nounwind74declare i32 @puts(ptr nocapture readonly) #375 76attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }77attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }78attributes #2 = { nounwind readnone }79attributes #3 = { nounwind }80 81!1 = !{!2, !2, i64 0}82!2 = !{!"omnipotent char", !3, i64 0}83!3 = !{!"Simple C/C++ TBAA"}84