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1; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s2; CHECK: q{{[0-3]}} = vand(v{{[0-9]+}},r{{[0-9]+}})3; CHECK: q{{[0-3]}} = vand(v{{[0-9]+}},r{{[0-9]+}})4; CHECK: q{{[0-3]}} = and(q{{[0-3]}},q{{[0-3]}})5 6target triple = "hexagon"7 8@g0 = common global <16 x i32> zeroinitializer, align 649 10; Function Attrs: nounwind11define i32 @f0() #0 {12b0:13 %v0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)14 %v1 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v0, i32 -1)15 %v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2)16 %v3 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v2, i32 -1)17 %v4 = tail call <64 x i1> @llvm.hexagon.V6.pred.and(<64 x i1> %v1, <64 x i1> %v3)18 %v5 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v4, i32 -1)19 store <16 x i32> %v5, ptr @g0, align 64, !tbaa !020 ret i32 021}22 23declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)24declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)25declare <64 x i1> @llvm.hexagon.V6.pred.and(<64 x i1>, <64 x i1>) #126declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #127 28attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }29attributes #1 = { nounwind readnone }30 31!0 = !{!1, !1, i64 0}32!1 = !{!"omnipotent char", !2, i64 0}33!2 = !{!"Simple C/C++ TBAA"}34