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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; Make sure we generate a hardware loop and pipeline the inner loop using4; 4 packets, which is equivalent to the hand-coded version.5 6; CHECK: loop0(.LBB0_[[LOOP:.]],7; CHECK: .LBB0_[[LOOP]]:8; CHECK: {9; CHECK: }10; CHECK: {11; CHECK: }12; CHECK: {13; CHECK: }14; CHECK: {15; CHECK: }16; CHECK: {17; CHECK-NOT: }18; CHECK: }{{[ \t]*}}:endloop019 20define void @f0(ptr noalias %a0, i32 %a1, i32 %a2, i32 %a3, ptr noalias nocapture %a4, i32 %a5, i32 %a6) #0 {21b0:22 %v0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 8388736)23 %v1 = zext i32 %a3 to i6424 %v2 = shl nuw i64 %v1, 3225 %v3 = zext i32 %a1 to i6426 %v4 = shl nuw nsw i64 %v3, 1627 %v5 = or i64 %v4, %v228 %v6 = or i64 %v5, 28147497671065829 tail call void asm sideeffect " l2fetch($0, $1)\0A", "r,r"(ptr %a0, i64 %v6) #2, !srcloc !030 %v7 = tail call i32 @llvm.hexagon.S2.ct0(i32 %a6)31 %v8 = add i32 %v7, 132 %v9 = lshr i32 %a1, %v833 %v10 = mul i32 %a6, 234 %v11 = mul i32 %v10, %v935 %v12 = sub i32 %a1, %v1136 %v13 = lshr i32 %v12, 137 %v14 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %v13)38 %v15 = icmp eq i32 %a2, 039 br i1 %v15, label %b11, label %b140 41b1: ; preds = %b042 %v16 = mul i32 %a3, 243 %v17 = icmp eq i32 %v9, 044 %v18 = icmp eq i32 %v11, %a145 %v19 = icmp ugt i32 %v12, %a646 %v20 = mul i32 %v9, 6447 %v21 = getelementptr i8, ptr %a4, i32 %v2048 %v22 = mul i32 %v9, 12849 %v23 = add i32 %v22, %a350 %v24 = getelementptr i8, ptr %a0, i32 %v2351 %v25 = getelementptr i8, ptr %a0, i32 %v2252 br label %b253 54b2: ; preds = %b10, %b155 %v26 = phi ptr [ %v25, %b1 ], [ %v90, %b10 ]56 %v27 = phi ptr [ %v24, %b1 ], [ %v89, %b10 ]57 %v28 = phi ptr [ %v21, %b1 ], [ %v88, %b10 ]58 %v29 = phi <16 x i32> [ undef, %b1 ], [ %v85, %b10 ]59 %v30 = phi <16 x i32> [ undef, %b1 ], [ %v84, %b10 ]60 %v31 = phi ptr [ %a0, %b1 ], [ %v86, %b10 ]61 %v32 = phi ptr [ %a4, %b1 ], [ %v87, %b10 ]62 %v33 = phi i32 [ 0, %b1 ], [ %v37, %b10 ]63 %v37 = add nsw i32 %v33, 264 %v38 = icmp ult i32 %v37, %a265 br i1 %v38, label %b3, label %b466 67b3: ; preds = %b268 %v39 = getelementptr inbounds i8, ptr %v31, i32 %v1669 tail call void asm sideeffect " l2fetch($0, $1)\0A", "r,r"(ptr %v39, i64 %v6) #2, !srcloc !170 br label %b471 72b4: ; preds = %b3, %b273 %v42 = getelementptr inbounds i8, ptr %v31, i32 %a374 br i1 %v17, label %b6, label %b575 76b5: ; preds = %b5, %b477 %v44 = phi ptr [ %v54, %b5 ], [ %v42, %b4 ]78 %v45 = phi ptr [ %v52, %b5 ], [ %v31, %b4 ]79 %v46 = phi ptr [ %v61, %b5 ], [ %v32, %b4 ]80 %v47 = phi i32 [ %v62, %b5 ], [ 0, %b4 ]81 %v48 = getelementptr inbounds <16 x i32>, ptr %v45, i32 182 %v49 = load <16 x i32>, ptr %v45, align 64, !tbaa !283 %v50 = getelementptr inbounds <16 x i32>, ptr %v44, i32 184 %v51 = load <16 x i32>, ptr %v44, align 64, !tbaa !285 %v52 = getelementptr inbounds <16 x i32>, ptr %v45, i32 286 %v53 = load <16 x i32>, ptr %v48, align 64, !tbaa !287 %v54 = getelementptr inbounds <16 x i32>, ptr %v44, i32 288 %v55 = load <16 x i32>, ptr %v50, align 64, !tbaa !289 %v56 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v0, <16 x i32> %v49, i32 1077952576)90 %v57 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v0, <16 x i32> %v53, i32 1077952576)91 %v58 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v56, <16 x i32> %v51, i32 1077952576)92 %v59 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v57, <16 x i32> %v55, i32 1077952576)93 %v60 = tail call <16 x i32> @llvm.hexagon.V6.vpackob(<16 x i32> %v59, <16 x i32> %v58)94 %v61 = getelementptr inbounds <16 x i32>, ptr %v46, i32 195 store <16 x i32> %v60, ptr %v46, align 64, !tbaa !296 %v62 = add nsw i32 %v47, 197 %v63 = icmp eq i32 %v62, %v998 br i1 %v63, label %b6, label %b599 100b6: ; preds = %b5, %b4101 %v64 = phi <16 x i32> [ %v29, %b4 ], [ %v55, %b5 ]102 %v65 = phi <16 x i32> [ %v30, %b4 ], [ %v53, %b5 ]103 %v66 = phi ptr [ %v42, %b4 ], [ %v27, %b5 ]104 %v67 = phi ptr [ %v31, %b4 ], [ %v26, %b5 ]105 %v68 = phi ptr [ %v32, %b4 ], [ %v28, %b5 ]106 br i1 %v18, label %b10, label %b7107 108b7: ; preds = %b6109 %v69 = load <16 x i32>, ptr %v67, align 64, !tbaa !2110 %v70 = load <16 x i32>, ptr %v66, align 64, !tbaa !2111 br i1 %v19, label %b8, label %b9112 113b8: ; preds = %b7114 %v71 = getelementptr inbounds <16 x i32>, ptr %v66, i32 1115 %v72 = getelementptr inbounds <16 x i32>, ptr %v67, i32 1116 %v73 = load <16 x i32>, ptr %v72, align 64, !tbaa !2117 %v74 = load <16 x i32>, ptr %v71, align 64, !tbaa !2118 br label %b9119 120b9: ; preds = %b8, %b7121 %v75 = phi <16 x i32> [ %v73, %b8 ], [ %v65, %b7 ]122 %v76 = phi <16 x i32> [ %v74, %b8 ], [ %v64, %b7 ]123 %v77 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v0, <16 x i32> %v69, i32 1077952576)124 %v78 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v0, <16 x i32> %v75, i32 1077952576)125 %v79 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v77, <16 x i32> %v70, i32 1077952576)126 %v80 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %v78, <16 x i32> %v76, i32 1077952576)127 %v81 = tail call <16 x i32> @llvm.hexagon.V6.vpackob(<16 x i32> %v80, <16 x i32> %v79)128 %v82 = load <16 x i32>, ptr %v68, align 64, !tbaa !2129 %v83 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v14, <16 x i32> %v81, <16 x i32> %v82)130 store <16 x i32> %v83, ptr %v68, align 64, !tbaa !2131 br label %b10132 133b10: ; preds = %b9, %b6134 %v84 = phi <16 x i32> [ %v75, %b9 ], [ %v65, %b6 ]135 %v85 = phi <16 x i32> [ %v76, %b9 ], [ %v64, %b6 ]136 %v86 = getelementptr inbounds i8, ptr %v31, i32 %v16137 %v87 = getelementptr inbounds i8, ptr %v32, i32 %a5138 %v88 = getelementptr i8, ptr %v28, i32 %a5139 %v89 = getelementptr i8, ptr %v27, i32 %v16140 %v90 = getelementptr i8, ptr %v26, i32 %v16141 br i1 %v38, label %b2, label %b11142 143b11: ; preds = %b10, %b0144 ret void145}146 147; Function Attrs: nounwind readnone148declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1149 150; Function Attrs: nounwind readnone151declare i32 @llvm.hexagon.S2.ct0(i32) #1152 153; Function Attrs: nounwind readnone154declare <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #1155 156; Function Attrs: nounwind readnone157declare <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32>, <16 x i32>, i32) #1158 159; Function Attrs: nounwind readnone160declare <16 x i32> @llvm.hexagon.V6.vpackob(<16 x i32>, <16 x i32>) #1161 162; Function Attrs: nounwind readnone163declare <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1>, <16 x i32>, <16 x i32>) #1164 165attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }166attributes #1 = { nounwind readnone }167attributes #2 = { nounwind }168 169!0 = !{i32 -2146401371}170!1 = !{i32 -2146401153}171!2 = !{!3, !3, i64 0}172!3 = !{!"omnipotent char", !4, i64 0}173!4 = !{!"Simple C/C++ TBAA"}174