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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; Verify __builtin_HEXAGON_V6_vd0 maps to vxor4; CHECK: v{{[0-9]*}} = vxor(v{{[0-9]*}},v{{[0-9]*}})5 6@g0 = common global <16 x i32> zeroinitializer, align 647 8; Function Attrs: nounwind9define i32 @f0(i32 %a0) #0 {10b0:11 %v0 = alloca i32, align 412 store i32 %a0, ptr %v0, align 413 %v1 = call <16 x i32> @llvm.hexagon.V6.vd0()14 store <16 x i32> %v1, ptr @g0, align 6415 ret i32 ptrtoint (ptr @g0 to i32)16}17 18; Function Attrs: nounwind readnone19declare <16 x i32> @llvm.hexagon.V6.vd0() #120 21attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }22attributes #1 = { nounwind readnone }23